delay-locked 中文意思是什麼
delay-locked
解釋
延遲鎖定的-
The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.
目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。 -
By complementing the proposed scheme with methods to estimate the fractional code delay, the acquisition unit an provide high quality delay estimates such that it can instead of the delay locked loop in the traditional ds receiver. after dispreading successfully, this dissertation introduces a method to estimate the doppler - shift directly from some samples based maximum likelihood estimation, and then revise it forwardly
在成功解擴之後，本文利用最大似然估計從l個樣點中直接估計出殘余多普勒頻偏，並進行前向頻偏校正，來代替傳統擴頻接收機中的科斯塔斯環，經模擬證明該方法的估計精度完全滿足解調的要求。 -
Firstly, the principle and realization of the step acquisition and delay locked loop are discussed
首先，論文討論了步進捕獲延遲鎖定環的原理及實現機理。 -
There are two uncertain factor about it : the phase of the pn code and the doppler - shift. after capturing the received signal successfully, the traditional ds receiver always uses a delay locked loop ( dll ) to synchronize the pn code and then uses a costas loop to realize the carrier synchronization. this complex closed - loop structure not only take long time to realize the synchronization, but also has the defect of “ hang up ”
傳統的擴頻接收機通常在捕獲偽碼信號后利用遲早門鑒相的延時鎖定環來實現偽碼的精同步，解擴后利用科斯塔斯環實現載波同步，這種閉環結構不僅同步時間長、結構復雜，而且鎖相環還存在所謂的「 hang - up 」現象。 -
Based on that and the actual request, the thesis focuses on two ways of frequency synthesis : phase - loop locked and phase - loop locked + direct digital synthesis. then it introduces the concepts of group - delay and all - pass network, analyzes the theory of equalizing the group - delay of filter by all - pass network, simulates the design and sums up a perfect designing and debugging precept
中頻群延遲的均衡通過全通網路來實現，文中給出了信號傳輸中群延遲的概念以及全通網路的概念，詳細分析了全通網路用作群延遲均衡器的設計原理，並對設計進行了計算機模擬，給出了滿足要求的設計方案。 -
The parallel scheme based on sliding correlation method is proposed in the simulation of acquisition. baseband fully time delay - locked pn code tracking loops are employed in tracking simulation
在對完全互補碼捕獲的模擬中，本文提出了基於滑動相關法的并行捕獲實現方案。 -
Chapter one introduces the recent development of usb2. 0 and the overall architecture of transceiver interface ; chapter two proposes the design flow and design style ; chapter three presents the whole system and module partition ; chapter four emphasizes on the dual - mode transmitter circuit, and gives out the simulation waveforms ; chapter five focuses on the design of over - sampling receiver and dll ( delay locked loop ) module ; chapter six designs the band - gap reference circuit. in the end, it concludes the design, and estimates the trend of usb. the dissertation is emphasized on dual - mode transmitter architecture, implementation of high speed dll using dba ( digital - based analog ) technology and a new design methodology for complex digital modules in mixed - signal circuit
本文第一章介紹了usb2 . 0的發展現狀和收發器介面晶元系統；第二章介紹了該晶元的設計流程和風格；第三章介紹了該介面晶元的總體構架以及模塊劃分；第四章著重介紹雙模發送器電路設計並給出了模擬驗證波形；接下來第五章分析了過采樣接收器的設計並對其中的dll （ delaylockedloop ）模塊設計進行了詳細的分析；第六章介紹了本晶元內置的基準電壓源的設計；最後對本文的設計一個總的回顧和總結，並展望下一代usb的發展方向。
分享友人