fault-tolerant multiprocessor system 中文意思是什麼
fault-tolerant multiprocessor system
解釋
容錯多處理機系統-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。 -
Consequently, an urgent problem is to ensure the tolerance of hardware error, to strengthen the tolerance of software error, to integrate hardware and software fault - tolerant technique in operating system level. based on the above analysis, this thesis researches the techniques of reliability and multi - processors system and proposes a fault - tolerance real - time embedded multi - processor system based upon the loosely coupled multiprocessor architecture
在此基礎上，本文對容錯關鍵技術和多處理器系統進行了深入地研究，結合多處理器結構和現代操作系統的分層結構思想，提出了一種基於松耦合多處理器體系結構的實時嵌入式容錯系統設計方案，以達到從整體上提高系統可靠性的目的。
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