fault-tolerant software 中文意思是什麼
fault-tolerant software
解釋
容錯軟體-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。 -
Focal point of this text promptly in how to realize the software programming in the fault - tolerant of parallel multi - processors system
本文的著重點是并行多處理器系統容錯的軟體實現。 -
The supervision tree is a hierarchical arrangement of code into supervisors and workers, making it possible to design and program fault - tolerant software
管理樹是一些管理者和工作者的分層排布代碼.它使得設計和編寫容錯軟體成為可能 -
First, this paper has discussed the hardware and software configuration of the dissimilar redundancy fault - tolerant computer system, and described how to realize this fault - tolerant system and proposed a reliability model based it. second, it has introduced the constitute and the principium of the mode select panel which we have manufactured
本論文首先論述了非相似余度容錯計算機系統的硬體和軟體結構，描述了該系統的容錯實現技術，並在此基礎上提出了一種適合於該系統可靠性分析的數學模型。其次介紹了所研製的模態選擇板的構成和工作原理。 -
So, in the design of highly reliable fadec system, it is greatly necessary to enhance research & development of fault - tolerant software system. in this paper, software technique applied to highly reliable fadec system is studied. the fadec system consists of hardware layer based on similarity redundancy technique and software layer based on dissimilarity redundancy technique
面對目前國內關于航空發動機高可靠性fadec軟體系統研究工作相對滯后的現狀，本文針對硬體層基於相似余度技術，軟體層基於非相似余度技術構成高可靠性fadec系統的相關軟體技術進行了研究。 -
Abstract : some ways of antiinterference about microcomputer test system for motor is presented, such as electricity supply, shield, ground connection, information connection, information passageway in hardware and the fault - tolerant techniques and digital filtering methods in system software. so the system has stable performance and safe work to strengthen antiinterference ability
文摘:對電機微機測試系統提出幾種抗干擾措施.通過對供電、屏蔽與接地及信息通道等硬體的抗干擾設計和在系統軟體中採用數字濾波及容錯技術，使原系統性能穩定，運行安全，以增強其抗干擾能力 -
The common language runtime greatly assists the design of fault - tolerant software by providing a model for notifying programs of errors in a uniform way
公共語言運行庫提供了一個模型，以統一的方式通知程序發生的錯誤，從而為設計容錯軟體提供了極大的幫助。所有的 -
To tolerate faults, the techniques rely on redundant implementations, which are n - modular redundancy for building fault - tolerant hardware and n - version programming or recovery blocks method for building fault - tolerant software
容錯的技術在於採用冗餘工具，也就是採用n模塊冗餘構造容錯硬體，採用n版本編程或恢復塊方法構造容錯軟體。 -
Hardware software fault - tolerant techniques like mirroring to protect the disks on which the database and transaction log information is stored
硬體/軟體容錯技術，例如鏡像，以保護存儲數據庫和事務日誌信息的磁盤。 -
This thesis introduces the conception of the system reliability, and analyzes some basic techniques for system reliability systematically, concludes the factors that influence the fault - tolerant real - time system : on the one hand, most of the fault - tolerance systems utilizes the hardware fault - tolerant technique, which improves the system reliability in a certain extent. however, this approach can only solve hardware error, and is helpless to software error. on the other hand, the real - time computing systems are designed decoupling between hardware and software, which is not beneficial for reliability design, especially for the tolerance design of software
本文首先介紹了系統可靠性的基本概念;詳細分析了基本的可靠性保障技術，特別是軟體容錯和硬體容錯的基本技術;歸納了制約容錯技術在實時系統中的應用的兩個核心問題:一是大多數容錯系統以硬體容錯為主，對于軟體錯誤無能為力;二是實時計算機系統設計中軟硬體耦合度低的特點不利於系統可靠性設計，特別是軟體容錯設計;導出了現代錯誤容忍設計急待解決的關鍵問題:確保硬體忍錯，強化軟體容錯，在系統級整合軟、硬體容錯。 -
Consequently, an urgent problem is to ensure the tolerance of hardware error, to strengthen the tolerance of software error, to integrate hardware and software fault - tolerant technique in operating system level. based on the above analysis, this thesis researches the techniques of reliability and multi - processors system and proposes a fault - tolerance real - time embedded multi - processor system based upon the loosely coupled multiprocessor architecture
在此基礎上，本文對容錯關鍵技術和多處理器系統進行了深入地研究，結合多處理器結構和現代操作系統的分層結構思想，提出了一種基於松耦合多處理器體系結構的實時嵌入式容錯系統設計方案，以達到從整體上提高系統可靠性的目的。 -
Then, two fault - tolerant - orient real - time operating system ( rtos ), which are tested as flight critical software applications and reliable, are presented. in addition, the synchronization between the two computers in fadec system, which includes synchronization of real time clock ( rtc ) and synchronization of task layer, is designed
基於這種全新系統結構，完成了fadec系統軟體非相似技術容錯結構系統設計；完成了高可靠性非相似嵌入式實時操作系統（ rtos ）的選型；完成了fadec系統雙機同步（包括時鐘級同步和任務級同步）設計。 -
Software fault - tolerant computing technology and method of reliability assessment
軟體容錯技術與可靠性評估方法 -
The system this paper has brought forward is a dissimilar redundancy fault - tolerant computer system, whose main structure used dissimilar cpus ( 180486 and 180960 ) to build its hardware system and n - version programming to build its software system
本論文所提出的是非相似余度容錯飛控計算機系統，其主要結構是採用非相似的cpu （ i80486和i80960 ）構成非相似余度計算機硬體系統，同時，運用n版本編程方法，構成它的軟體系統。
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