floating point 中文意思是什麼
floating point
解釋
浮點法-
Feu floating point execution unit. this performs floating point related calculations for both existing scalar instructions along with support for some of the new simd - fp instructions
Feu浮點執行單元。與支持simd _ fp指令的現有規模指令一起執行浮點相關的計算。 -
This is known as floating-point representation.
這就是所謂的浮點表示法。 -
Imprecise serialization of floating - point values has a similar problem
浮點值的不精確序列化有類似的問題。 -
Design of a parameterized floating point multiplier
一種浮點乘法器的參數化設計 -
The operand is a 32 - bit ieee floating point number
該操作數為32位ieee浮點數。 -
The operand is a 64 - bit ieee floating point number
該操作數為64位ieee浮點數。 -
Fpu : floating - point processing unit
浮點處理單元 -
2 montoye r k, hokenek e, runyon s l. design of the ibm risc system 6000 floating - point execution unit. ibm journal of research and development, 1990, 34 : 59 - 71. 3 oberman s. floating - point arithmetic unit including an efficient close data path
我們採用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該演算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且演算法本身沒有造成新的關鍵路徑。 -
As of the middle of 2001, the world s fastest computer can perform, on average, about five trillion floating point operations per second, or 5 teraflops. the machine that ranks 500th averages about 55 gigaflops
在2001年中期，世界上最快的計算機可以平均每秒執行5萬億次浮點運算，也就是5 teraflop （ teraflop每秒1萬億次浮點運算） 。 -
Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design
Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。 -
In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree
特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。 -
These are typically things like bootup sequences and device drivers, but also may include floating - point code including long long types
這些通常是啟動次序和設備驅動程序，不過也可能包括浮點代碼（包括long long類型） 。 -
Editing floating - point values can result in minor inaccuracies because of decimal - to - binary conversion of fractional components
編輯浮點值時，由於要將小數部分從十進制轉換為二進制，因此所得的結果可能存在微小誤差。 -
There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way
Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。 -
This paper studies fpu ' s algorithm, data - path, control - path, and implements the integration of the powerpc603e system. this thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded powerpc603e microrpocessor
論文的研究工作包括： ?研究浮點演算法，主要包括加減法、乘法、除法、開平方以及cordic （ coordinaterotationdigitalcomputer ）演算法。 -
Prior to google, alan spent 15 years at digital compaq hp s western research laboratory where he worked on a variety of chip design and architecture projects, including the microtitan floating point unit, bips the fastest microprocessor of its era
在他加入google之前， alan在digital compaq hp的西部研究室工作了15年，致力於各種晶片的設計及製造專案，其中包括當時最快的微處理器： microtitan floating point unit ， bips 。 -
It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc
它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。 -
In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future
第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga -
The work in this thesis was part of a national 05 " project which task was designing the " longtengrl " microprocessor. there are four parts in " longtengrl " microprocessor : integer execution unit ( ieu ), floating point unit ( fpu ), memory subsystem unit ( msu ) and bus interface unit ( biu )
本論文完成存儲子系統單元的設計與實現、 「龍騰r1 」系統的集成、存儲子系統單元的驗證以及在「龍騰r1 」存儲子系統基礎上進行了tracecache的研究，其中重點討論存儲子系統的設計與實現。 -
Converts the specified floating point value to
將指定的浮點值轉換為
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