gate current 中文意思是什麼
gate current
解釋
門電流-
Tidal current control gate
潮流控制閘 -
By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability
然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。 -
Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet
基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高 -
With the continued scaling - down of mosfet, the ultra - thin gate oxide causes some serious problems of devices. the ultra - thin sio2 dielectrics cause significant leakage current, consequently increases standby power of device. meanwhile, the reliability of gate dielectrics is also degraded
當mosfet器件按比例縮小到70nm尺寸以下時，傳統的sio _ 2柵介質的厚度將需要在1 . 5nm以下，如此薄的sio _ 2層產生的柵泄漏電流會由於顯著的量子直接隧穿效應而變得不可接受，器件可靠性也成為一個嚴重的問題。 -
During the circuit design, the author analyzed the basic principle of the direct current motor, pwm control, h - bridge power driver, and two control techniques of h - bridge power drive circuit, designed its general structure, so the feasibility of the design is confirmed. then, reference, oscillator, power dmos gate drive circuit ( charge pump, bootstrap ), and dead time generation circuit are designed and analyzed in the sub - circuits. a current - controlled oscillator is presented in this thesis
在電路設計中，作者介紹了直流電機的工作原理和數學模型、脈寬調制（ pwm ）控制原理、 h橋電路基本原理和h橋功率驅動電路的兩種控制模式，設計了驅動電路的總體結構，給出了電路的功能模塊，確定了設計的可行性，然後在子電路模塊中，重點分析設計了基準源電路、振蕩器電路、高端功率管柵驅動電路（電荷泵及自舉電路） 、低端功率管柵驅動電路和死區時間產生電路。 -
The activity - based current extraction algorithm has been improved in gate capacitance calculation
此外，對基於活動率的電流提取器進行改進，提高了等效門級電容的計算準確度。 -
A particular over - current protection and drive circuit is given, the impact of resistance between gate and emitter on gate voltage dropping is discussed, and an adjustable gate - emitter resistance circuit is put forward
設計了過電流保護驅動電路，討論了柵射集電阻對降柵壓過程的影響，並提出一種可變柵射集電阻電路。 -
In gan hemt drain pulse current collapse experiments, drain current under pulse condition collapsed about 50 % than direct current condition and the pulse signal frequency affected little on current collapse. when gate voltage is small, the relationship between pulse width and drain current is i0 ( + t / 16 )
在ganhemt漏極脈沖電流崩塌測試中，發現脈沖條件下漏極電流比直流時減小大約50 % ;脈沖信號頻率對電流崩塌效應影響較小;當柵壓較小時，隨著脈沖寬度的改變漏極電流按i0 （ + t / 16 ）的規律變化。 -
Under pulse condition, charging and discharging of surface states between gate and drain induce gan hemt current collapse
脈沖條件下， ganhemt電流崩塌效應主要由柵漏之間表面態充放電引起。 -
In this paper, the theory of negatively charged surface states is used to investigate dynamic breakdown characteristics and the increase of gate - drain breakdown voltage as well as the reduction of saturated drain - source current after sulfur passivation. the measure which can improve the stability of sulfur passivation is proposed
本論文通過對gaasmesfet擊穿機理和硫鈍化機理的研究，用負電荷表面態理論，解釋了gaasmesfet動態擊穿特性及硫鈍化后柵漏擊穿電壓增大、源漏飽和電流減小的機理，提出了改善硫鈍化穩定性的措施。 -
In gan hemt gate pulse experiments, drain current under pulse conditon collapsed about 47 % than direct current condition and the pulse width affected little on current collapse. the relationship between drain current and pulse frequency is ncoxw [ m + ( n + k ? ) vgs + ( n + k ? ) vgs2 ] ( vgs - vth ) 2 / l
在ganhemt柵極脈沖電流崩塌測試中，觀察到柵脈沖條件下漏極電流比直流情況下減小了47 % ;隨著信號頻率的改變，漏極電流按ncoxw [ m + （ n + k -
Secondly, the transient characteristics of fn tunneling and hot hole ( hh ) stress induced leakage current ( silc ) in ultra - thin gate oxide are investigated respectively in this dissertation
其次，本文分別研究了fn隧穿應力和熱空穴（ hh ）應力導致的超薄柵氧化層漏電流瞬態特性。 -
According to the diverse current state of a tilting gate, the flux calculation program was worked out to calculate the flux at different current state of the gate and to protract the curves of flux to upper reaches of the gate
根據翻板閘門的不同水流流態，編制過閘流量計算程序，計算各流態的過閘流量，並繪制了過閘流量與上游水位關系曲線。 -
The large gate current brings out a lot of questions such as thermal stability, thermal dissipation, lifetime etc, so, it affects the device ' s function and the device ca n ' t work normally
如此大的柵電流，將會產生很多嚴重的問題，如熱穩定性、散熱、壽命等問題，嚴重地影響著器件性能，使器件不能正常工作，以致限制了集成電路的進一步發展。 -
We can obtain the trap density by measuring the change of gate voltage of mos capacitance under constant current stress and the change of high frequency c - v curve before and after the stress
該方法根據電荷陷落的動態平衡方程，測量恆流應力下mos電容的柵電壓變化曲線和應力前後的高頻cn曲線變化求解陷階密度。 -
With the research on hfoxny gate dielectrics, it can reduces leakage current and increase crystallizing point ; our research can help to realize the leakage current mechanism and silc effect of hfo2, futher more it can offer us direction on optimize the fabrication process
結果表明，與hfo :相比，氮化的hfo :具有小的漏電流。我們的研究結果有助於進一步了解hro :柵介質的泄漏電流機制和silc效應的特徵，為進一步優化hfo :高k柵介質的制備工藝提供指導。 -
The thyristor can be trigged into the on - state by applying a pulse of positive gate current for a short duration provided that the device is in its forward blocking state
如果是處于正向阻斷狀態，只要在門極提供一個短暫的正脈沖，晶閘管就會導通。 -
With respect to a bipolar transistor, the condition in which the gate current equals or exceeds the value necessary to provide full emitter collector conduction
就雙極型晶體管而言，其門電流等於或超過必要的值，使發射極集電極充分導通的一種狀態。 -
Once the device begins to conduct, it is latched on and the gate current can be removed
一旦器件（晶閘管）導通，門極電流即可去掉。 -
Since metal - oxide - semiconductor ( mos ) device appeared, integration of integrated circuit ( ic ) expands as moore law. meanwhile the dimension of device scales down, the thickness of sio2 gate dielectric shrinks as the same law. but as the thickness of sio2 gate dielectric reaches at isa, the gate current rises very quickly and reaches at 1 10a / cm2
自從金屬-氧化物-半導體（ mos ）器件出現以來，集成電路的集成度按照摩爾定律增加，相應地，器件的物理尺寸按照等比縮小的原則不斷縮小， sio _ 2作為柵介質的厚度不斷縮小，特徵尺寸在0 . 1 m以下的集成電路要求sio _ 2柵介質的厚度小於1 . 7nm 。
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