gate output 中文意思是什麼
gate output
解釋
門電路輸出-
A pulse to gate the output of a core memory sense amplifier into a trigger in a register
一種只讀存儲器，其中的內容可以擦除，使存儲器成為空白狀態。 -
A model of the interface state density distribution near by valence band is presented, and the dependence of the threshold voltage on temperature, the c - v characteristics and the subthreshold characteristics are predicted exactly with this model ; the effects of s / d series resistance on the output characteristics, transfer characteristics and effective mobility of sic pmosfets are analyzed. thirdly, the output characteristics and the drain breakdown characteristics are modeled with the procedure medici. the output characteristics in the room temperature and 300 ? are simulated, and the effects of gate voltage. contact resistance, interface state and other factors on sic pmos drain breakdown characteristics are analyzed
提出了一個價帶附近的界面態分佈模型，用該模型較好地描述了sicpmos器件閾值電壓隨溫度的變化關系、 c - v特性曲線以及亞閾特性曲線；分析了源漏寄生電阻對sicpmos器件輸出特性、轉移特性以及有效遷移率的影響；論文中用模擬軟體medici模擬了sicpmos器件的輸出特性和漏擊穿特性，分別模擬了室溫下和300時sicpmos器件的輸出特性，分析了柵電壓、接觸電阻、界面態以及其他因素對sicpmos擊穿特性的影響。 -
By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability
然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。 -
The methods that can efficiently suppress the disturbance on gate of switching component of the inverter - bridge are synthesized. a dual - inductor output filter is employed to improve electromagnetic interference ( emi ), due to turn - on or turn - off of the power switches of the inverter, which may be lead loads into trouble
本文詳細論述了1kva25hz新型鐵路信號電源和2kva高頻在線式ups的設計和調試工作，總結了幾種能夠有效抑制逆變橋功率開關管門極干擾的措施，並且運用一種雙電感結構的輸出濾波器來改善由逆變器功率管在開關過程中產生的、影響負載設備正常工作的電磁干擾。 -
The feedback of the output voltage is the major control loop. to achieve better frequency response and disturbance rejection of the input voltage, a input voltage feed - forward system is introduced in control loop. the duty - cycle of pwm applied at the gate of power mosfet is modulated by both input and output voltage
該晶元採用的控制方式為電壓型pwm （脈沖寬度調制， pulsewidthmodulation ）控制方式，以輸出電壓反饋作為主要控制參量，同時為了提高晶元對輸入電壓擾動的響應速度，採用了輸入電壓前饋方法，將輸入電壓因素引入了反饋控制環中，通過對輸入輸出電壓的檢測，控制加在功率mos管柵極電壓上矩形脈沖的占空比，進而調節輸出電壓。 -
The output signal can then be amplified ( possibly with a logic gate at this point ) to drive the converters
電路輸出的信號需要放大后再使用（例如用邏輯門） 。 -
Fan - out refers to the number of standard loads ( inputs ) that the output of a gate can be connected to without impairing its normal operation
輸出端數量就是指在不削弱其功能的前提下，輸出柵門所能連接的標準荷載的數量。 -
The resonance network is connected to the gate, then the output and input matching network is designed to satisfy the oscillation criteria. then harmonic balance method is used to analysize and optimize the output power and phase noise. to minimize the load pulling effect a buffer amplifier is designed to isolate the oscillator and the load
本文在場效應管fet柵極上加上諧振網路（諧振網路是通過cst模擬得到的，它是串聯反饋迴路，介質工作在te01模，對于其後的fet ，它又相當於一個帶阻濾波器） ，然後設計輸入輸出匹配電路，使電路結構滿足起振條件，之後繼續用諧波平衡法模擬和優化，使振蕩器輸出功率合適，相位噪聲很低。 -
Hfets ( doped channel ) : concept ; i - v model including velocity saturation ; gate 2 characteristics ; output conductance ; applications of strained layers
基本概念，電流-電壓模型，其中包括速度飽和，閘極特性，輸出電導，應變層的應用。 -
An electrical gate or mechanical device which implements the logical or operator. an output signal occurs whenever there are one or more inputs on a multichannel input. an or gate performs the function of the logical " inclusive or operation "
一種實現邏輯「或」演算法的門電路或機械器件。當在其多通道輸入端有一個或多個輸入時就產生一個輸出信號。 「或」門實現邏輯「或操作」的功能。同orelement 。 -
Abstract : constant components and output opened ports in the result of high - level synthesis lead to explicit redundancy in gate - level technology mapping. explicit redundancy can not improve the performance, but increases power consumption, enlarges circuit area and decreases its testability, so it should be removed. this paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability
文摘:高級綜合結果中常量元件和輸出懸空埠導致門級工藝映射結果中存在顯式冗餘.顯式冗餘無助於提高電路性能，反而增加功耗，降低電路的可測試性，使電路面積增大，應予消除.文中提出了顯式冗餘的隊列循環優化演算法，完全消除了此類冗餘，從而有效地減少了生成電路的基片面積，提高了電路的可測試性 -
From the view point of the foundation of dft ( which includes the testable measure of gate - level circuits, the testable and controllable measure of functional - level, the flow and methodology of dft and so on ), the author introduce some common testing technology such as scan and bist in modern times. especially the boundary scan technology has been widely adopted in the dft of vlsi. with the special controller, the testing vector could be scanned to the corresponding ports of inner cores from the testing input ports, and the response could also be shifted to the testing output ports
本文從可測性設計的基礎理論出發（包括門級電路的可測性測度、功能級上的可測性和可控性、可測性設計的流程和方法等） ，介紹了現代常用的可測性技術，比如：掃描技術、內嵌自測試技術等，特別是邊緣掃描技術已經廣泛地應用到vlsi的可測性設計之中，它通過特定的控制器，從相應的測試輸入埠將測試向量掃描至芯核所對應的管腳，再將結果從相應的測試輸出埠掃出。 -
According to the following design theory : the dsp calculates in real time and produces three phases spwm waves to control the on or off of the 6 igbts in ipm respectively. ipm then inverts the commutated single phase direct current ( insulated gate bipolar transistor ) into three phases alternating current. when modulated signals of spwm are changed, the on - off time of switches also changes, so as to the voltage and frequency of output signals
本文提出了一種基於dsp （數字信號處理器tms320f240 ）的通用的三相間接變頻電源系統，利用分段同步調製法和混合查表法，實時計算不同頻率下的采樣周期、電壓幅值、輸出脈寬，產生雙極性spwm波形，經驅動放大後用于ipm （ intelligentpowermodule ）中的絕緣柵雙極型晶體管柵級驅動，以控制電源的輸出電壓和頻率，實現變頻電源的智能數字控制。 -
2. the control signals couple through the capacitance of the switches to the output, the dynamic error caused by the parasitic gate ? drain feedthrough capacitance is significantly lowered by the use of a reduced voltage swing at the input of the switches
2 .差分開關的控制信號會通過晶體管的寄生電容耦合到輸出，從而影響dac的動態性能，設計中通過降低控制信號電壓的方法來解決這個問題。
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