hardware cache 中文意思是什麼
hardware cache
解釋
硬體緩沖存儲器-
He job of cache coherency is done partially by the hardware and partially by the operating system
保證高速緩存一致性的工作由硬體和操作系統共同分擔。 -
Some hardware configurations share common resources like an l3 l4 cache
有些硬體配置將共享l3 / l4緩存之類的公共資源。 -
This paper introduced a much more precise sampling method using cpu hardware performance counters ( chpc ) to provide cpu data like instruction cycles, cache misses, branch prediction, and so on, and given detail scene of software status
摘要引入了基於cpu硬體性能計數器的性能數據採集和分析方法，從軟體運行時刻的細粒度參數入手分析軟體運行時刻的性能表現，從而更為準確地反映系統實際的動態運行狀態。 -
Some provide hardware to automatically clear cache tags, while others require software looping to invalidate cache tags
有一些實現提供了自動清除高速緩存標簽的硬體，而其他實現需要使用軟體循環來使高速緩存標簽無效。 -
3 thoroughly reviewed memory bandwidth requirement of sma processor and difference of various instruction fetch policies. to improve cache performance under sma model, the paper introduces hardware software co - operative optimization
3針對多線程模式下訪存負荷加重的問題，為sma模型設計了軟硬體協同預取機制，並為sma模型設計了cachefilter來消減無效預取。 -
In the memory access subsystem design, on the basis of deeply discussing three kernel problems encountered in cache design, this paper presents a li cache model with virtual index and physical tag, using a hardware - based method to solve the synonym problem, and adopting l2 cache " s initiative requesting for the li cache " s snoop service to keep the consistency between li cache and l2 cache, then takes li data cache as an example to illustrate the li cache implementation
在訪存子系統的設計中，深入研究並解決了cache設計中的三個核心問題：採用虛地址索引、實地址tag ，用硬體方式解決synonym問題，以l2cache向l1cache主動請求snoop服務的方式實現兩級cache間的一致性。在此基礎上，給出了一個l1d - cache原型。 -
The research area covered by the thesis includes embedded system design, hardware infrastructure of embedded gis system, architecture of nand flash, error detect code / error check code and there algorithm, journal file system, gis file index, wear leveling for nand flash, file system page cache and write delay, dynamic compression in file system etc. first, the thesis first analysis the embedded gis status in quo, technology background, difficulty it facing
本文研究領域涉及嵌入式系統開發、嵌入式gis系統軟硬體框架、 nand晶元體系結構、差錯檢測差錯校驗（ edc ecc ）演算法、日誌文件系統、文件索引、晶元擦寫平衡、文件系統頁面cache與延遲寫技術、文件系統實時壓縮等技術。 -
Comparing with other cache store miss policies, cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases memory queue full rate without increasing hardware overhead
與傳統的cache寫失效處理策略相比， cache自適應寫分配策略硬體代價小，避免了不必要的數據傳輸，降低cache污染，減少存儲管理隊列阻塞的頻率。 -
And hardware / software coverification is carried out to guarantee the correctness of design. in the design of hardware of memory system, according to the system specification, we select the appropriate memory capacity, sram block, associativity and the placement of cache in the pipeline
在存儲系統的硬體設計中，始終以性能指標作為依據，克服了存儲器容量、庫單元規格選擇、聯合度的選擇和cache在流水線中的位置選擇等困難，設計出了符合指標要求的指令存儲系統。 -
Pipelining and parallel technology, accompanying with fast fifo as cache memory, instead of direct program operation, are adopted in the scheme and increase the transmitting speed dramatically ; fpga ( field programmable gate array ) is applied to realize the complex control logic of the system and makes it integrative, flexible and fast ; 386ex based embedded system, along with vxworks real - time operating system is introduced to substitute the microcontroller based system to simplify the hardware design and enhance the overall performance of ssr, and will make the system more easier to be applied to the projects in the future
該設計方案採用了流水線和并行技術，配以快速fifo緩存的方式取代了直接對flash進行編程的方式，極大地提高了閃存晶元存儲數據的速率；採用fpga技術實現系統的主要控制邏輯，集成度高、靈活性好、速度快；採用基於386ex的嵌入式系統及基於vxworks的嵌入式實時操作系統，取代單片機系統及其編程，提高了系統的整體性能，減輕了硬體設計的負擔，且使系統研發的延續性好。 -
On the software side, compiler inserts prefetch instructions explicitly ; on the hardware side, an sma cache filter is added to cut down unnecessary prefetch. 4 guided by feedback - based optimization strategy, the paper presents a dynamic profile based continuous optimization framework - smarcof
4研究了基於動態輪廓信息的軟硬體聯合持續優化機制，並在dlx模擬器的基礎上設計並實現了一個完整的指令級模擬平臺和基於上述優化規則的編譯框架smarcof 。 -
Hi the hardware pat, we design the units of high - speed cache and pipeline, which are absent in other similar products ( in today ' s market )
在硬體開發中，論述了目前國內市場上同類產品所沒有的高速緩存cache和流水線等部件的研究與設計。
分享友人