high-intermediate-frequency receiver 中文意思是什麼

high-intermediate-frequency receiver 解釋
高中頻超外差式接收機
  • high : adj 1 高的〈指物，形容人的身高用 tall〉；高處的；高地的。2 高級的，高等的，高位的，重要的。3 高尚...
  • intermediate : adj 中間的，居間的。 The intermediate class （船的）特別三等。 An intermediate compound 中間化合...
  • frequency : n. 1. 屢次，頻仍，頻繁。2. （脈搏等的）次數，出現率；頻度；【物理學】頻率，周率。
  • receiver : n 1 接受者。2 收稅人，收稅官。3 招待人。4 窩家，收買賊贓的人。5 應戰者。6 【法律】破產案產業管理...
  1. The rf receiver consists of rf front end and baseband regulation module. the high - intermediate - frequency superheterodyne structure is adopted in the final scheme. the fine sensitivity of the receiver is achieved by two cascaded lna in the front of the system

    系統採用超外差式變頻結構設計，兩級低噪聲放大單元級聯保證了接收機靈敏度，兩級增益控制單元實現了所要求的接收機動態范圍，並且整機的線性度也得到了保證。
  2. The high - intermediate - frequency superheterodyne structure with twice conversions is used. three cascaded agc units applies in the receiver system, one of them is used as the choice, for realizing a high dynamic range while the linearity of the system is well guaranteed

    系統採用了兩次變頻超外差式結構設計，第一中頻為高中頻。另外系統還包含了三級自動增益控制單元，其中一級agc作為選項，實現了較大的動態范圍，並且整機的線性度也得到了保證。
  3. This thesis deals with design and application of a multiprocessor made of four dsps in monitoring receiver. the broadband monitoring receiver requires a kind of chip with high performance because of complicated intermediate frequency signal processing. the author selects a kind of digital signal processor called adsp21160. during the process of design, the author uses cpld, fpga and some special cpus to finish signal, processing in the monitoring receiver. cluster multiprocessor based on vxibus made of four adsp21160 is put forward. the task distribution of four dsps is solved too. furthermore, data transition methods between chips at a high speed through link ports and chip extension mode using external port are recommended. the author debugs, emulates the program in one adsp - 21160 ez - kit lite and simulates the multiprocessor program in visualdsp + +

    本文主要探討了監測接收機中多dsp處理模塊的設計與應用，寬帶監測接收機的中頻處理數據量大、實時性高，這樣，對dsp晶元提出了很高的要求，作者通過比較選擇了最適用於監測接收機的數字信號處理器adsp21160 ，並結合使用了cpld 、 fpga以及一些專用的cpu來完成監測接收機中的數據處理。作者提出了由四片adsp21160組成的簇式多dsp處理模塊的結構並配以了vxi總線，論述了簇式結構的特點，解決了多dsp處理模塊中四片adsp21160的任務分配問題。
  4. The current commercial ddc lack of high speed data processing and fast tune change, which limit the develop of the wideband digital receiver, so special digital intermediate frequency system is needed

    目前商用的數字下變頻器由於缺乏高的數據速率和快的調諧時間，使得寬帶數字接收的發展受到限制，這就需要有專門的數字中頻系統來解決此問題。
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