instructions cache 中文意思是什麼

instructions cache 解釋
指令緩存
  • instructions : 幾點說明
  • cache : n. 1. （探險者等貯藏糧食、器材等的）暗窖，密藏處。2. 貯藏物。3. 【計算機】高速緩沖內存。vt. 1. 貯藏；密藏；窖藏。2. 【計算機】把…儲存到硬盤上。
  1. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  2. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  3. Table 9. cache management instructions

    表9 .高速緩存管理指令
  4. The powerpc architecture contains cache management instructions for both application - level cache accesses

    Powerpc體系結構包含了面向應用級高速緩存訪問的高速緩存管理指令。
  5. The packet unit has a queue into which fetched cache blocks are stored containing instructions

    封裝單元中具備了一個佇列，用以儲存讀取到的資料。
  6. If a cache is used to store both instructions and data, it is called a unified cache

    如果一個隱藏所用來儲存指導和數據，它叫做一個被統一的隱藏所。
  7. It can also be applied to multithread scheme by adding thread identifier. our experiment results indicate that about 25. 8 % of all memory reference instructions in spec cpu2000 benchmarks are executed in parallel by adopting adaptive stack cache with fast address generation. on average 9. 4 % data cache miss is reduced

    Speccpu2000程序運行結果表明，採用快速地址計算的自適應棧高速緩存方案， 25 . 8 %的訪存指令可以并行執行，數據高速緩存失效率平均降低9 . 4 % ， ipc值平均提高6 . 9 % 。
  8. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed

    指令讀取器產生讀取位址以供快取記憶體讀取快取區塊內的指令。
  9. Cache management instructions are listed in table 9

    高速緩存指令在表9中列出。
  10. On the software side, compiler inserts prefetch instructions explicitly ; on the hardware side, an sma cache filter is added to cut down unnecessary prefetch. 4 guided by feedback - based optimization strategy, the paper presents a dynamic profile based continuous optimization framework - smarcof

    4研究了基於動態輪廓信息的軟硬體聯合持續優化機制，並在dlx模擬器的基礎上設計並實現了一個完整的指令級模擬平臺和基於上述優化規則的編譯框架smarcof 。
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