internal bus 中文意思是什麼
internal bus
解釋
內部總線-
Fiber optics mechanization of an aircraft internal time division command response multiplex data bus
光纖化的飛機內部時分制指令響應式多路傳輸數據總線 -
Internal control bus ibc
內部控制總線 -
This layout can stop the internal arc fault expansion ; can avoid harmful moisture, small animal and dusty interferences. it also has good perfomiance and high reliability. because the heat cannot transmit to the outside of the bus room, a good operation environment for the low space can be obtained
主母線室置於箱體頂部一個單獨的金屬封閉的間隔內，並與10kv開關室、儀表室等間隔相互獨立，為同類產品首創；這種結構可以防止內部電弧故障的擴大化，避免「火燒聯營」事故；防護性能好，防潮、防小動物侵害、防積塵，運行可靠；由於母線室的隔熱作用，為下層空間創造了一個較好的運行環境。 -
A circuit is designed to define the odd and even line to meet the layout ' s simplification requirement. to make full use of the system resource, an auto - test circuit is designed with test vector can be given through the internal bus and result vector can be detect by system
為了充分利用了嵌入式晶元豐富的系統資源，設計了簡單實用的自測試電路，其測試向量和結果向量都可以通過總線被系統直接讀取，系統執行相應的指令就可以完成相應的自測試過程。 -
Host bus adapter with 2 internal ports
帶2個埠的主機總線適配器 -
This scheme fully considers the internal structure of jx5 microprocessor, at the same time, the processor ’ s processing ability, address and data bus architecture is efficiently utilized. so with the minimal testing cost, a strong fault testing and trace debugging ability is provided to meet the jx5 processor ‘ s testing demand
該方案充分考慮了jx5的內部結構，有針對性的選擇了一系列成熟可靠的可測性技術和方法，經過精心組合搭配，並充分利用jx5所具有的處理能力和cpu特有的地址、數據總線結構，在盡量少的增加測試開銷的前提下，提供了很強的故障測試和追蹤調試能力，很好的滿足了jx5對測試的需求。 -
Rdram has the virtue of being an extremely high - bandwidth memory solution, so it can keep that 10 - channel dmac ( which can manage 10 simultaneous bus transfers ) busy and those internal caches fed
Rdram的優點就是是它是能夠使用非常高帶寬的內存解決方案，所以它可以使得10通道的dmac （同時能夠處理10條并行的總線傳輸事務）和緩存處于非常高效的狀態。 -
The internal processor bus described in sec. xx is connected to the external processor bus by a set of bus buffers located on the microprocessor integrated circuit
Xx節所描述的內部總線通過一組位於微處理器集成電路內的總線緩沖器與外部總線連接。 -
Bbl back - side bus logic. logic for interface to the back - side bus for accesses to the internal unified level two processor cache
後端總線邏輯。訪問內部統一二級處理器緩存的後端總線介面邏輯。 -
5 have a good cooperation with internal bus and coordinate ， supervise and evaluate the external contractors
對內，做好與各業務部的協調配合工作；對外，監管外協承包商、並做好評估管理工作 -
The procedures of iterative equivalent and internal bus modification are followed to gain the convergence of distributed reactive optimization
如此交替等值和內點法修正，直到分散式無功優化計算收斂。 -
The auto - test process could be done by several instructions " executed. results of the ip core ' s simulation shows the adc can achieve a 10 - bit resolution. system has 8 input channel and 5 sample period selection with the control of internal bus
對該ip核的全局模擬結果表明，所設計的模數轉換器可以達到10位的精度，可以通過系統總線信號對8路信號輸入通道以及5種采樣速率進行選擇控制，可以通過系統指令完成模數轉換器的自測試功能。
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