interrupt controller 中文意思是什麼

interrupt controller 解釋
中斷控制器
  • interrupt : vt. 1. 阻止；妨礙；遮斷。2. 打斷（別人的話等）；中斷；打攪。3. 截斷。vi. 打擾，（別人談話時）插嘴。
  • controller : n 1 管理人，主管人。2 （會計的）主計人，檢查員；〈英國〉（特指宮廷、海軍等的）出納官〈常作 comptr...
  1. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  2. Apic advanced rogrammable interrupt controller

    高級可編程中斷控制器
  3. Apic : advanced programmable interrupt controller

    高級程序中斷控制器
  4. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  5. During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed

    在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。
  6. The down - up design includes the researches of decoder schematics, controller schematics, pipeline schematics, bus schematics, stack schematics and interrupt schematics. the thesis content and outcome of research are beneficial to the design of a cpu design project. at the same time, these contents are beneficial to the design of a microcontroller

    整個正向設計由於採用了簡化的措施，還存在一些不足，因此從逆向設計的角度，研究了pic微控制器晶元中處理器的電路實現結構，主要包括譯碼電路和控制器電路的實現結構，流水線電路的實現結構，處理器內總線的實現結構，以及堆棧和中斷電路這些與處理器電路有密切相關性的子電路單元。
  7. Adsl line test is a part of our design, so it must under the control of higher level controller and there are multi - task for higher level controller to attemper. in the last part of article the programming methods becomes stress of our topic. on base of analyzing interrupt response time and task - switch time and task - attemperring time this article implements a method of transplanting ucos to c51 controller

    Adsl線路測試部分是作為一個功能模塊存在於設計中的，它必須受到上層控制器的控制，而上層控制器有多個任務要執行，本文最後一部分微控制器編程理論，重點分析微控制器的多任務消息驅動機制編程方法和嵌入式操作系統移植技術，在分析兩種編程方法的任務響應和任務切換及中斷響應時間的基礎上，設計出了一套ucos移植到c51控制器上的方法。
  8. Supplemental facilities include debug unit for real - time debugging, high resolution tick timer, programmable interrupt controller and power management support

    輔助功能包括用於實時調試的調試單元，高解析度嘀噠計數器，可編程中斷控制器和電源管理。
  9. Could not initialize the interrupt controller

    不能初始化中斷控制器。
  10. Research on a kind of real - time interrupt controller

    一種應用於嵌入式實時系統的中斷控制器研究
  11. Interrupt controller with 9 external inputs

    中斷控制器：具有
  12. Programmable interrupt controller

    可程序規劃岔斷控制器
  13. Pic programmable interrupt controller

    可編程中斷控制器
  14. This paper describes the implementation method of the software and hardware about the embedded system. first, designed the embedded system ’ s hardware plat that have the s3c44b0x as core ; second, replanted the embedded operation system : c / os - ii, applied it ’ s interrupt controller and synchronization in between tasks ; finally, achieved the harmonious operation between the software and hardware

    首先，設計了以s3c44b0x為核心的嵌入式系統硬體平臺;其次，移植了c / os - ii嵌入式操作系統，並充分運用了它的中斷控制和任務的通信與同步;最後，實現了軟硬體的協同操作。
  15. The host controller will automatically post an interrupt at a specified interval

    主控器會以特定的間隔自動發出一個中斷。
  16. Can ( controller area network ) is famous for its excellent real - time ability and high performance to cost ratio. can is a typical event - triggered field - bus, and can applications exhibit low bandwidth utilization ratio. a time - triggered scheduling method for the can 2. 0 has been presented by use of hardware periodical interrupt of micro - controller and software programming technique

    （ 2 ） can （ controllerareanetwork ）總線技術實時性好，性價比高，但這種事件觸發型現場總線網路利用率較低，針對can總線在分散式系統中的應用，利用微控制器的硬體定時器，結合軟體編程，提出了一種can總線的時間觸發調度方法。
分享友人
分享到 Line

分享到臉書