layout versus schematic (lvs) 中文意思是什麼
layout versus schematic (lvs)
解釋
布局與原理圖比較-
At last, the layout is verified with cadence verification tools, dracula. drc ( design rule cherker ) and lvs ( layout versus schematic ) have been done successfully, which improve the feasibility of the layout design. so the whole ic design flow, from the front end to the back end of a circuit design, is completed
接著應用無錫上華標準0 . 6umcmos工藝提供的元器件模型參數進行了電路模擬,並根據尺寸設計規則設計了整體電路的的版圖,最後運用cadence中的版圖驗證工具集dracula對電路版圖成功地進行了drc ( designrulecherker ) 、 lvs ( layoutversusschematic )驗證,證明了電路版圖設計的可行性,完成了ic設計從前端到後端的設計流程。
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