level cache 中文意思是什麼
level cache
解釋
二級緩存-
Hibernate, like jdo, has a two - level cache
像jdo一樣， hibernate擁有兩級緩存。 -
Flexible method of the audit storing enhances the dependability of audit information. two - level real - time alarm and second analysis of audit information enhance the utility of audit information. and the audit cache reduces the time spending caused by auditing
通過靈活的審計存儲方法，提高了審計信息的可信度;同時，通過審計的兩級實時報警和對審計信息的事後分析，提高了審計信息的利用率。 -
Through the implementing of kernel level file and cache mechanism at the client side, this newly proposed distributed network file system provides seamless network file access and reduces the performance decline caused by network transmission. utilizing the concept of logic block server, it provides the reliable data block storage and implements redundant storage capacity. utilizing the concept of the index server, it provide s the cost of the greatly for server and network during data access process and realizes the computing with balancing capacity
在客戶端通過實現內核級文件的調用和緩沖機制，實現了文件的無縫網路存取，並減少由於網路傳輸帶來的性能下降的影響；利用邏輯塊服務器實現邏輯塊的冗餘存取，實現數據塊的安全存放；利用索引服務器進行負載均衡計算，實現資料存取的較低網路和服務器開銷；利用索引服務器實現服務器組的零管理，使該系統具有高效性、穩定性和可伸縮性。 -
Excepting algorithms self, the software performance analysis and optimization always relate to the multi - hiberarchy storage archtechture, trying to utilize the nearside storage media such as register or level 1 cache and reduce actions on farside storage, and try to reach a linear performance, i. e. the computing performance only relate to the speed of cpu clock
現在的軟體性能分析及其相關的性能優化，除了程序本身演算法之外，幾乎所有的分析和優化都是在這樣一個多級的存儲體系結構上進行的，試圖盡可能地利用近端的存儲，期望達到一個接近線速的計算性能，即計算的性能僅由cpu的處理速度決定，與其他外設和數據存儲無關。 -
The powerpc architecture contains cache management instructions for both application - level cache accesses
Powerpc體系結構包含了面向應用級高速緩存訪問的高速緩存管理指令。 -
Secondly, he establishes a rule table of vehicles " behaviors based on analyzing them. the table can simplify the model of vehicle ' s following and lane changing so that it will shorten the time of simulation. and thirdly, by using the cache technology of level - two time cell, the author solves the conflict, which arises from the limited memory and the masses of cache that is needed to get the better precision in simulation
本文在系統設計中，用匝道控制和主線控制相結合的方法，進行高速公路全線交通的綜合控制，優化控制效果；根據車輛行為分析，建立了車輛行為規則表，將車輛跟馳模型和換道模型簡化為車輛行為表，減少了模擬時間；採用二級時間片的緩沖技術，解決了模擬過程為達到較高模擬精度所需的大量緩存與有限內存空間的矛盾。 -
Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here
該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。 -
Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture
現代計算機和cpu設計中， cpu片內的寄存器、一級高速緩存（ level1cache ）和二級高速緩存（ level2cache ） ，主板上的三級高速緩沖，再加上主存，外存（硬盤、軟盤、電子盤等） ，構成了現代計算機的多級存儲體系結構。 -
At the machine level, volatile and synchronization often end up getting translated into the same cache coherency primitives, so there effectively is
在機器級，易變的和同步的內容通常在最後會被翻譯成相同的緩存一致原語，所以這里會有 -
The dm642 uses a two - level cache - based architecture, level 1 cache is composed of a 16 - kbit l1p ( level 1 program cache ) and a 16 - kbit l1d ( level 1 data cache ), level 2 cache consists of 256 - kbit memory space that is shared between program and data space
同時，研究了消除欠采樣噪聲演算法，並實現其處理功能。本文提出的系統設計方案，實現了高速、穩定、靈活的視頻採集處理播放平臺，可以高速而穩定的持久運行，達到了設計的要求。 -
Cache adaptive write allocate policy collects fully modified blocks in miss queue. fully modified blocks are written to lower level memory based on non - write allocate policy which can switch to write allocate policy adaptively
該策略在訪存失效隊列中收集全修改cache塊，對全修改cache塊採用非寫分配策略，並能夠自適應地切換為寫分配策略。 -
In fact, it is more effective in system level. low power technique of microprocessor is composed of clock - gating, close part of cache, and dvs ( dynamic voltage scaling ). low power technique of peripheral equipments design is composed of closing the idle parts of the equipment and degrading the service quality satisfied with lowest requirement
處理器的低功耗設計大都採用系統級，其技術主要包括:門控時鐘技術， cache部分關閉技術，動態電壓縮放dvs （ dynamicvoltagescaling ）技術;外圍設備低功耗設計包括:關閉設備空閑部件;在滿足基本性能要求前提下，降低外圍設備的服務質量。 -
The cache on the apparatus is a one - level cache that is size of 8 bytes
實驗儀的cache為一級cache ，容量共8個位元組。 -
When you specify both an application - level cache policy and a request - level cache policy, the request - level policy is used
如果您同時指定了應用程序級緩存策略和請求級緩存策略，應採用請求級緩存策略。 -
Using application - level cache profiles, a feature that enables you to define output caching settings for an entire application
使用應用程序級別緩存配置文件，此功能使您能夠定義整個應用程序的輸出緩存設置。 -
Setting application - level caching enables you to change cache behavior from a single configuration file rather than editing the
設置應用程序級別緩存使您能夠從單個配置文件更改緩存行為，而無需編輯各個頁面的 -
Bbl back - side bus logic. logic for interface to the back - side bus for accesses to the internal unified level two processor cache
後端總線邏輯。訪問內部統一二級處理器緩存的後端總線介面邏輯。 -
Cache items with this priority level are the most likely to be deleted from the cache as the server frees system memory
在服務器釋放系統內存時，具有該優先級級別的緩存項最有可能被從緩存刪除。 -
Cache items with this priority level are the least likely to be deleted from the cache as the server frees system memory
在服務器釋放系統內存時，具有該優先級級別的緩存項最不可能被從緩存刪除。 -
The server uses multi - level cache technology and has high stability and concurrence. e - sibucongkan ' s browser provides powerful displaying function and auxiliary research tools
文中設計的四部叢刊電子版瀏覽器提供了強大的瀏覽顯示功能和輔助研究的工具。
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