level logic circuit 中文意思是什麼
level logic circuit
解釋
電平邏輯電路-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。 -
Based on many other circuit formats, a new kind of logic - level circuit representation, called unified middle - level circuit format ( umcf ), is defined in this paper, in which some special operations on circuit related with power estimation and low power design. umcf can not only interchange circuits of different formats, but also convert circuits to hspice acceptable files, which can be used for transistor level power estimation
本文結合多種不同的電路格式，自主定義了一種邏輯級電路的中間表示形式（稱為umcf ）和一系列極具特色的與低功耗技術相關的操作，它不但可以實現與其他多種電路格式之間的相互轉換，還可以將電路直接轉換成hspice可以接受的文件，進行晶體管級的電路功耗估計，這樣可以在公認的高精度的功耗模擬器上，對本文的結果進行有效的驗證。 -
The proposed 64 bits high performance alu is optimized at algorithm level, logic level, circuit level and layout level, and is implemented in 0. 18 m cmos process. furthermore, the testing technique of the alu is discussed. this thesis mainly contributes to the following aspect : 1
文章從部件的演算法、邏輯結構、電路參數、物理版圖等多個層次進行設計優化，在0 . 18 mcmos工藝下實現了一款64位高性能算術邏輯部件，並對該部件的測試方法進行研究。 -
Because the signal which serial interface output of mcu is ttl logic level, it is essential to transform ttl electrical level to rs - 232 electrical level when the mcu is communicated with pc. in this paper the universal rs232 / 485 electrical level converting circuit board is designed. it can realize data transmission by the two communication level manner
因為單片機的串列輸出介面輸出的電信號是ttl電平，這樣在和上位機通信時需要通過轉換電路對其電平進行轉換，所以在本課題中設計了通用的rs - 232 485電平轉換電路板，可以實現兩種不同電平的數據傳輸，通過最後的實驗驗證，該電路板能實現所要求的功能，傳輸信號可靠準確。 -
Low power vlsi designs can be achieved at various design levels, which rang from circuit, logic, architecture and algorithmic ( behavioral ) levels to system level, according to the down - top design flow
超大規模集成電路低功耗設計可以在不同的設計層次進行考慮，自下而上分可以分為：物理層、邏輯層、結構層、演算法（行為）層和系統層。 -
In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter
在電路模塊分析中，重點介紹了語音的輸入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等，並且給出了在硬體電路設計和調試過程中的問題與解決辦法。
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