logic circuit design 中文意思是什麼
logic circuit design
解釋
邏輯電路設計-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。 -
This paper presents the logic circuit design of ccu for lx - 1164 cpu chip, for ccu, data and instructions are stored in separate data and instruction caches
本人有幸在夏宏博士的指導下參加這一工程，承擔lx ? 1164cpu的高速緩存控制器（ ccu ）的邏輯設計和功能模擬。 -
In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical
在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。 -
The logic design of sequence circuit of welding supply based on gal
的焊接電源時序電路設計 -
By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument
本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。 -
Secondly, the composition and function of expander board is introduced, the paper describes a detail developing process of selecting component, design interface circuit, protract pcb with protel and design pci interface logic and user ' s logic. with ahdl and max + plus. in addition this paper discusses how to debug pci board, and give the simulation waveform and the result of debug. on the base of all functions is ture, this paper introduce the config registers and memory of bu - 61580, realize the interrupt function and communication based on mil - std - 1553b
首先分析了擴展板的組成、功能，對pci介面邏輯和擴展板的內部邏輯進行詳細設計，並根據其資源要求進行器件選擇，然後使用protel工具進行電路板的製作。另外，本文還介紹了擴展板的調試方法，給出了邏輯模擬波形和調試結果。在此基礎上，本文闡述了協議晶元的配置方法，實現了1553b通訊擴展板間的通訊及中斷功能，達到了開發技術指標。 -
This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15
該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。 -
Application of programmable logic device in circuit design of competitive answer machines
可編程邏輯器件在搶答器電路設計中的應用 -
Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly
Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。 -
Higher mathematics, visual basic programming design, fundamentals of law, linear algebra ， fundamentals of, computer application, physical education, computer networks and communication, c + + with object - oriented, programming, data structures, philosophy and political theory, programming in c language, operating systems, software test technology, relations on business, digital logic circuit, international software development, social analysis and government policy, introduction to java visual foxpro database systems and program design, e - business, introduction to programming with an application framework, software engineering, introduction to web page design and programming
高等數學、大學計算機應用基礎、程序設計教程軟體工程、用戶界面設計、電子商務、軟體工程、數據庫應用與程序設計、線性代數、編碼理論基礎、信息管理基礎、軟體成本估算、質量管理、計算機軟體技術基礎、實用軟體體系基礎、大型軟體體系結構、軟體測試技術、客戶關系管理、電子商務、國際化軟體開發、現代項目管理、計算機網路與通信。 -
Design basis of combinational logic circuit
組合邏輯電路設計基礎 -
To reduce the size and increase the reliability of the control card, lattice company ? isplsi chip is used to realize the digital logic circuit. its insystem programmable ability makes it easy to realize the design of digital logic circuit
6軸伺服控制卡上，使用lattice公司的isplsi器件實現數字邏輯電路設計，降低了板卡的設計尺寸，增加了電路板的可靠性和設計靈活性。 -
Tms320c5402dsp was used in the design to replace six scm those was used in the automatic biochemical analyzer now and to control system, cpld epm7128 offer logic circuit to the system. a 16 - bits high - speed a / d conversion device a / d976a replaced a / d574 to complete digital - analog conversion
本系統設計中採用一片高性能的dsp （數字信號處理器） tms320c5402代替了目前生產的全自動生化分析儀的六個單片機完成系統控制，用可編程邏輯器件epm7128提供所需的邏輯信號，採用16位高速a d轉換器ad976a取代以往的ad574完成模數轉換。 -
Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches
速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。 -
According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design
為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。 -
Particularly set forth scm control circuit, principle and realization process of dc electromotor in creeping machine, the design of logic circuit and principle of interface card, the design of precise location installation, the choice of sensor, its principle and realization process, including the concrete process of realization by software
詳細闡述了爬行器中直流電動機驅動裝置的單片機控制電路設計、工作原理及實現過程；介面卡邏輯電路的設計和工作原理；精確定位裝置的設計、傳感器的選用、工作原理，包括各項工作的具體軟體實現過程。 -
The logic analysis and circuit design of vme bus interface iogic
總線介面邏輯分析和電路設計 -
The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation
在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。 -
In order to make full behavior simulation of sigma - delta modulator, the noise models have been set, taking into account most of the sigma - delta modulator ’ s non - idealities and the final result supports the noise models. last, the main circuits of modulator have been designed, such as operational amplifier, comparator and clock generator, the design principle of noise - killed logic circuit has been presented. these circuits have been simulated
調制器的噪聲模型，考慮了影響調制器性能的一些主要非理想因素，通過模擬驗證了噪聲模型的正確性;最後，設計實現了結構中的主要電路，如運放、比較器、時鐘產生電路，闡述了噪聲抵消邏輯電路的工作原理，利用hspice和cadencespectre對各電路進行了模擬，驗證其功能。 -
In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter
在電路模塊分析中，重點介紹了語音的輸入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等，並且給出了在硬體電路設計和調試過程中的問題與解決辦法。
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