logic chip 中文意思是什麼
logic chip
解釋
邏輯集成電路-
This paper presents the logic circuit design of ccu for lx - 1164 cpu chip, for ccu, data and instructions are stored in separate data and instruction caches
本人有幸在夏宏博士的指導下參加這一工程，承擔lx ? 1164cpu的高速緩存控制器（ ccu ）的邏輯設計和功能模擬。 -
By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument
本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。 -
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
Secondly, the paper describe the principle of atm network, and the function of ' sar " ( segmentation and reassembly ) and the format of packet aal5, and introduce the basic idea of ipoa, and the design project and implementing of the control chip. later, the paper introduce the logic function and operational principle of packet buffer control chip and prove the feasibity and correctness of the arithmetic. at last the paper introduce crc - 32 arithmetic based on look up and implement it with hardware
接著詳細論述了核心路由器atm網路實現的原理，包括「 sar 」 （ segmentationandreassembly ）功能和aal5報文的格式， ipoa基本思想，以及控制晶元的設計方案和實現途徑等。然後又論述報文緩存區控制晶元的工作原理和邏輯功能等，並對演算法的可行性，正確性等進行論證。最後介紹了一種基於查表的crc - 32演算法的原理及其硬體實現。 -
As key technology of the single chip calculator, the highly integrated dynamic cmos logic implement and the micro program design are now owned only by the developed countries and kept in secret. based on the conjunction of " top - down " and " bottom - up " design approach, the hardware system and micro program design of the calculator is thoroughly studied in this paper, and finally has been mastered
本論文以香港興華半導體公司的計算器單晶元c9821為藍本，採用了自頂向下和從底向上相結合的方法，對計算器單晶元的硬體電路設計和軟體編程方法進行了深入的研究與剖析，終于掌握了這種晶元的設計技術，並對c9821進行了功能的改進與完善。 -
By achieving the thesis, the subject of the chip ' s logic control is deeper going
通過對各部分的設計，進一步對單片機的邏輯控制方面進行研究，並應用於實踐。 -
The thesis discusses on how to research and then design the led video panel system, which is a typical product of computer digital video system, by using the pld chip as the main control logic
本論文討論用pld晶元作為主要控制邏輯來設計計算機數字視頻系統的一個典型應用型產品? ? led視頻電子顯示屏系統的研製方法。 -
Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co. and the detailed analyses of typical examples are also given
結合altera公司classicep610晶元的結構，研究了將演化演算法應用於函數級數字組合邏輯電路的硬體演化，並且對典型實例進行了詳細分析。 -
This software system of chip simulation ' s main function is simulate the main logic circue chips, 8088cpu, memory, registers, data _ bus, address _ bus, control _ bus and other chips. this function is based on the object - oriented technology, construct the chip object by the chip classes that we defined. because this system need to simulate the detail function of computer hardware, so this system simulate the 8088cpu ' s order system, support the basic compile languages. one of the feture of this system is the simulation of a static memory, the room of the memory can be configured by testers from 1k to 64k
由於本系統在模擬過程中需要完全模擬計算機硬體的工作原理，因此本系統還模擬了8088cpu的基本指令系統，支持基本的匯編指令，在實驗過程中可以由實驗者輸入相應的匯編指令以執行操作，並查看各晶元器件的引腳參數變化情況。本系統模擬的一個特點是動態模擬了存儲器的大小，存儲器容量可以由實驗者根據需要自己設置，范圍從1k到64k 。 -
With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit
在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。 -
The hardware of the system is composed of a high - speed optical - isolator circuit, a first - in / first - out dual - port memory buffer circuit, a pci interface chip ql5032, and a logic control circuit
系統的硬體部分是由高速光電隔離電路，雙埠fifo存儲緩沖電路， pci總線介面電路ql5032及邏輯控制電路等組成。 -
To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation
論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。 -
To reduce the size and increase the reliability of the control card, lattice company ? isplsi chip is used to realize the digital logic circuit. its insystem programmable ability makes it easy to realize the design of digital logic circuit
6軸伺服控制卡上，使用lattice公司的isplsi器件實現數字邏輯電路設計，降低了板卡的設計尺寸，增加了電路板的可靠性和設計靈活性。 -
Pld refer to the programmable logic device. it is a kind of chip that can be written the design of integrated circuits into its logic arrays
Pld是指可編程邏輯器件，是一種可將集成電路的設計用編程的方式寫入到其邏輯陣列結構中的一種晶元。 -
There are six sub - modules in it : single - chip unit, data transfer unit, parallel data transfer / receive unit, serial data transfer / receive unit, system reset management and system power unit. this paper studies the design and realization of net interface module, mainly discusses design of data transfer unit ' s logic and the improvement of single - chip unit ' s software
論文首先從系統設計思想出發，對網路介面模塊的總體設計實現進行了研究，接著對作者主要研究的軟硬體分工協同設計中的軟體完善部分，邏輯設計部分，以及最後的邏輯測試、系統測試進行了重點論述。 -
4. through using the concept of logic balance, a high performance telecommunication switch network test chip is accomplished by using xilinx virtex 300e - 6 and the working clock frequency is up to 125mhz. this chip can give an exact test for the network delay time, throughput, network delay time dither, rate of errors and lost data
4 ）結合邏輯平衡的思想，採用xilinxvirtex300e - 6器件，為一家著名的通訊技術有限公司設計了速度達125mhz的交換網測試晶元，能夠對交換網的吞吐率，網路延時，網路延時抖動，數據包錯誤率，包丟失率等進行嚴格的測試，並根據當前網路的流量大小自動調節網路負載。 -
The main works were listed below : 1. as the core of image tracker, the advanced dsp technology ( adsp - ts201 ) and the programmable logic device ( ep1s40f1020 chip ) were combined together to make certain that instruction was completed within single instruction period
主要體現在下面幾點: 1 .圖像跟蹤器的硬體平臺以先進的dsp技術（ adsp - ts201 ）和可編程邏輯器件（ stratix系列的ep1s40f1020晶元）為核心，構成實時的圖像跟蹤處理器，使得指令可在單指令周期內完成運算。 -
With the exist of fpga chip ep1k30tc144 - 3, several hardware functions are realized in the chip, such as sample controlling logic, fifo inside, the connection circuit with pc, the connection circuit with mpu, the connection circuit with keyboard
系統採用了fpga晶元ep1k30tc144 - 3 ，並且在晶元內集成了采樣控制邏輯，內置hfo ，上位機介面，單片機介面以及鍵盤介面等多個功能模塊，使得數據採集卡的結構大大簡化。 -
The time division circuit and latch counter are integrated in one chip of programmable logic device, which makes the size greatly decreased
同時採用cpld晶元實現了時間分割電路和計數鎖存電路，有效地減小了電路體積。 -
With the help of newly developed advance electronics design automation ( eda ) technology, some roles and tens or hundreds of components of traditional instruments could be replaced or redesigned by means of large scale programmable logic chip ( cpld / fpga ) with the characters of the high integration, designed with hdl ( hardware description language ) and supporting iap ( in application programming ) and isp ( in system programming )
而隨著eda技術的飛速發展，大規模可編程邏輯晶元cpld fpga應運而生。這類晶元可以替代幾十甚至上百塊通用ic晶元，而且，因其可用硬體描述語言進行晶元設計、支持在線編程和在系統編程等優點而備受青睞。
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