loop-locked 中文意思是什麼
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Chapter 3 discusses the modules used in the fh - mpsk and fh - / 4dqpsk systems. these modules include : duc / ddc ( digital up converter / digital down converter ), nyquist flitter, burst start detection, interpolation module, pll ( phase locked loop ), pll error extraction, initial phase correction and the coding and decoding for tcm
第三章主要討論了跳頻模式下fh - mpsk和fh - 4dqpsk系統中各個模塊的設計，這些模塊包括：上下變頻器、奈奎斯特濾波器、信號到達檢測、插值模塊、通用環路、各環路誤差提取方法、初始相位校正和tcm編譯碼。 -
Pll - qpsk, phased - locked loop quadrature phase shift keying
鎖相環四相相移鍵控 -
Pll - qpsk phased - locked loop quadrature phase shift keying
鎖相環四相相移鍵控 -
This paper illuminates theory, structure, spectrum distribution, merits and defects, especially spurs of direct digital synthesis ( dds ), and it then introduces phase locked loop ( pll ) theory
對dds的結構、優缺點、頻譜分佈，特別是雜散性能進行了詳細的闡述。接著，又介紹了鎖相環（ pll ）的原理。 -
The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.
目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。 -
The carrier wave is modulated directly by the baseband signal at several frequency point in l band and s band. firstly, this paper clarifies the theory of i / q modulation, elaborates evm and acpl, and analyzes the effect of amplitude and phase unbalance and dc offset on evm. secondly we review the basic principle of phase locked loop and it ’ s composing parts, including the basic conception and design method of pll frequency synthesizer, especially introduce the charge pump pll frequency synthesizer in detail
首先，在闡述i / q正交調制基本原理的基礎上，通過對誤差矢量和鄰近通道功率泄漏的詳細分析，定性、定量地討論了各種非理想電路因素（如相位不平衡、幅度不平衡、直流偏差等）對調制器性能的影響;其次，介紹了鎖相環的工作原理和基本組成部分，包括鎖相環的設計和環路濾波器的設計，特別詳述了電荷泵鎖相頻率源;第三，介紹了採用直接調制技術模擬衛星信號的射頻前端的設計;最後，對整個直接射頻調制系統進行測試，結果基本上達到了課題要求。 -
By complementing the proposed scheme with methods to estimate the fractional code delay, the acquisition unit an provide high quality delay estimates such that it can instead of the delay locked loop in the traditional ds receiver. after dispreading successfully, this dissertation introduces a method to estimate the doppler - shift directly from some samples based maximum likelihood estimation, and then revise it forwardly
在成功解擴之後，本文利用最大似然估計從l個樣點中直接估計出殘余多普勒頻偏，並進行前向頻偏校正，來代替傳統擴頻接收機中的科斯塔斯環，經模擬證明該方法的估計精度完全滿足解調的要求。 -
Because massive harmonic interference in the electrical network, it causes signal - sampling to include the very big harmonic in the measurement system, for eliminating measurement result influence by harmonic, the paper has an in - depth study of fourier transformation harmonics analysis measurement principle, analysis the forming reasons of frequency spectrum leakage and railing effect during measurement, achieves phase locked loop and frequency multiplier technique to realize integer - period synchronous sampling and eliminate impact of frequency spectrum leakage and railing effect in the result of measurement, and investigates in depth theory on phase locked loop and frequency multiplier technique, gives the method of realizing phase locked loop and frequency multiplier technique
由於電網中存在大量的諧波干擾，導致測量系統中取樣信號也含有很大的諧波，為了消除諧波對測量結果的影響，論文深入研究了傅立葉變換諧波分析法的測量原理，分析了測量中頻譜泄漏和柵欄效應形成的原因，提出了採用鎖相環倍頻技術實現信號的整周期同步采樣，消除頻譜泄漏和柵欄效應對測量結果的影響，並對鎖相環倍頻技術的理論進行了深入研究，給出鎖相環倍頻技術的實現方法。 -
A multi - layer charge - pump phase - locked loop behavioral model
一種電荷泵鎖相環的多層行為級模型 -
3. with comprehensive improvement of transponder including structural adjustment to lna ; optimization of ( phase locked loop ) pll filter ; structural adjustment to the transmitter and phase error adjustment to the intermediate frequency demodulation circuit, we have successfully enhanced sensitivity, expanded dynamic range, increased transmitting power and improved the spectrum purity ; decreased capture time for pll ; improved the signal quality after demodulation ; reduced its volume and power consumption. 4
3 、對通信機的全面改進，包括lna結構的調整、鎖相環環路濾波器的優化、發射部分結構的調整以及中頻解調電路的相差調整，提高了系統的接收靈敏度、改善了本振的頻譜純度、減少了鎖相環的鎖定時間、使中頻解調后的信號質量大為提高，同時還減少了體積、節約了系統的功耗。 -
An application of lmx2306 in the frequency synthesizer based on the phase - locked loop
超高頻接收機中鎖相環的設計 -
Since commercial pll ic came out, phase - locked - loop frequency synthesis has become widely accepted. but when narrow frequency - step is required, the loop bandwidth has to decrease while cannot meet the demand of frequency - hopping speed
數字鎖相集成器件出現以來，鎖相式頻率合成器得到迅速發展，但是當需要窄頻率步進時，環路帶寬需要降低，致使鎖定時間變長，不能滿足快速跳頻的要求。 -
It has been an important component of communication, radar, instrument, high - speed computer and navigation equipment. fractional - n phase locked loop ( fnpll ) frequency synthesis has been appeared in recent years
頻率合成器是一種相位鎖定裝置，是通訊、雷達、儀器儀表、高速計算機和導航設備中的一個重要組成部分。 -
The actively and passive mode - locked fiber ring laser and two types of photonic switching, slalom ( semiconductor laser amplifier loop mirror ) and uni ( ultrafast nonlinear interferometer ) were developed. this thesis presented the principle and the requirements for the optical of frequency - shift sampling module under common conditions
研製了作為光取樣脈沖源的主動鎖模和被動鎖模光纖激光器；半導體光放大器環鏡及超高速非線性干涉儀的光子開關，並進行了頻差法光取樣、異步光取樣及基於時分光取樣的光子模數轉換的實驗研究。 -
A phase - locked - loop - based model reference adaptive system for speed estimation of sensorless induction motor drives
一種基於鎖相環原理的參考模型自適應感應電機轉速估計方法 -
In this thesis, phase - locked loop ( pll ) technogies are used to acquire phase of fundamental current in bais current, which enhances the detecting precision of bais current. and we want the phase of bais current and the phase of system current is the same, so this thesis think of locking the phase of bais current which based on this theory to sure the security and the reliability of apf
本文採用鎖相技術，以獲得畸變電流中基波電流的相位，進一步提高了畸變電流的檢測精度，並據此原理考慮鎖定補償電流的相位，使補償電流與系統電流相位同步，保證apf安全可靠運行。 -
For keeping the frequency and phase synchronous to the grid, a pll ( phase locked loop ) is necessary
為了使並網電流和電網電壓同頻、同相，需要使用鎖相環技術。 -
Implementation of fpga based three phase phase - locked loop system
的三相鎖相環實現 -
Based on that and the actual request, the thesis focuses on two ways of frequency synthesis : phase - loop locked and phase - loop locked + direct digital synthesis. then it introduces the concepts of group - delay and all - pass network, analyzes the theory of equalizing the group - delay of filter by all - pass network, simulates the design and sums up a perfect designing and debugging precept
中頻群延遲的均衡通過全通網路來實現，文中給出了信號傳輸中群延遲的概念以及全通網路的概念，詳細分析了全通網路用作群延遲均衡器的設計原理，並對設計進行了計算機模擬，給出了滿足要求的設計方案。 -
The system that electrical power is supplied by silicon - controlled, speed abjusted by direct current double loop - locked and controlled by microcomputer is the high acurracy digital system following the input signal
摘要微機控制的晶閘管供電的雙閉環直流數字調速系統是高精度復現輸入信號的數字隨動系統。
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