lower gate 中文意思是什麼

lower gate 解釋
下游閘門
  • lower : adj 〈low 的比較級〉1 較低的。2 下級的,低級的。 lower animals 下等動物。3 南部的。 in lower Manh...
  • gate : n 1 大門,扉,籬笆門,門扇。2 閘門;城門;洞門;隘口,峽道。3 【冶金】澆注道,澆口,切口;【無線...
  1. The lower part of the gate is stone, while on top is the " belvedere of the five phoenixes " where the emperor appeared on important occasions, and where the last emperor abdicated to ho chi minh ' s revolutionary government in 1945

    門較低處是石頭,上頭有鳳凰樓,這里是古代皇室偶爾會來的地方,這里也是末代皇帝於1945年退位讓給胡志明革命軍政府的地方。
  2. I had coasted along the lower wall of the orchard - turned its angle : there was a gate just there, opening into the meadow, between two stone pillars crowned by stone balls

    我信步朝果園的矮墻走去,在拐角處轉了彎,這里有一扇門,開向草地,門兩邊有兩根石柱,頂上有兩個石球。
  3. Applying silicon gate technology, the chip has a lower value in power consumption than the products made by aluminum gate technology

    由於採用硅柵工藝,該晶元比市場上曾經流行過的鋁柵產品功耗更低。
  4. Xing su ( microelectronics and solid state electronics ) directed by prof. lin chenlu the fast development of information technology requires integrated circuit to be greater integrated, faster functioned, and lower power - consumed, that lead to continuous shrinkage of mos and dram feature size. and under this trend the thickness of mos gate dielectrics ( sio2 ) would soon scale down to its physical limit

    日益增長的信息技術對更高集成度、高速、低功耗集成電路的需求,驅使晶體管的尺寸越來越小,隨之而來的問題是作為mos柵氧化物和dram電容介質的sio _ 2迅速減薄,直逼其物理極限。
  5. ( 4 ) the running state and hydraulic property of the hydraulic automatic tilting gate with connecting lever and rolling wheel were analyzed. the open - door curve, start - up water level and shutdown water level were ascertained, then the influence of lower reaches of a river to the running of a tilting gate was analyzed

    ( 4 )析闡述了連桿滾輪式水力自動翻板閘門的工作狀態與水力特性,推求了閘門的開門曲線、啟門水位和回關水位,並分析了下游水位對翻板閘門運行的影響。
  6. Fix that lower gate

    修好下面那道門了?
  7. The experimental results illuminate the hierarchical test generation algorithm can greatly decrease the scale of test sets ( about 66 % ), but the fault coverage and time performance are lower than gate - level test generation

    實驗數據表明分層測試產生演算法能大大壓縮電路測試集(約為66 ) ,而故障覆蓋率有略微下降,時間性能也有些許降低。
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