memory architecture 中文意思是什麼
memory architecture
解釋
存儲器體系結構- memory : n. 1. 記憶；記憶力；【自動化】存儲器；信息存儲方式；存儲量。2. 回憶。3. 紀念。4. 死後的名聲，遺芳。5. 追想得起的年限[范圍]。
- architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
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Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel
這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。 -
This method can save the space of memory and reduce the computation time. because only the parameters of scattering centers are stored and genetic algorithm is used to search for aspect angle, the method is very suitable for the employment in real - time and restrictive environment. in chapter 3, the architecture of mmw seeker is studied
該方法以目標多散射中心理論為基礎，只需要存貯目標的三維散射模型參數，需要的存貯量較少；與常規的全姿態角匹配識別方法比較，基於目標散射模型的匹配識別方法，由於利用了遺傳演算法的全局尋優能力，計算量較小。 -
Risc processors generally feature fixed - length instructions, a load - store memory architecture, and a large number of general - purpose registers and / or register windows
Risc處理器一般的特徵是固定長度的指令集，一個負載儲備存儲結構，和大量通用寄存器，及寄存器窗口。 -
Many mcus use the harvard architecture, in which the program is kept in one section of memory usually the internal or external sram
很多mcu使用harvard體系，程序保存在內存的一段中（通常是內部的或外部的sram ） 。 -
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
Once these changes ( dual mode, privileged instructions, memory protection, timer interrupt ) have been made to the basic computer architecture, it is possible to write a correct operating system
一旦對一個基本的計算機體系結構完成了以上修改（雙模式、特許指令、內存保護、定時器中斷） ，就有可能寫出正確的操作系統。 -
With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit
在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。 -
A novel flash memory, which uses the source induced band - to - band tunneling hot electron ( sibe ) injection to perform programming, and a pmos selected divided bit - line nor ( pnor ) array architecture are originally introduced in this dissertation
本論文首次提出了一種採用源極誘導帶帶隧穿熱電子注入（ sourceinducedband - to - bandtunnelinghotelectroninjection ）進行編程操作的新型快閃存儲器技術和一種pmos選擇分裂位線nor （ pmosselecteddividedbit - linenor ）快閃存貯陣列結構。 -
Cluster system is one of the hot spots in the research area of high performance computer, while system area network ( san ) that used to connect nodes is considered to be the key point in the cluster system the aims of this paper are to study dedicated high performance san network based on distributed shared memory architecture, and set up cluster system with high price performance ratio the main work and originalities in this paper list as followings : 1
群機系統是高性能計算機研究領域的熱點之一，而用於連接群機系統內部結點的系統域網路（ san ）是群機系統研究的關鍵。本文在分佈共享存儲器結構的基礎上研究高性能專用san網路，構建高性能/價格比的群機系統。本文的主要工作和創新點如下： 1 -
The on - chip memory performance of embedded systems directly affects the system designers decision about how to allocate expensive silicon area. a novel memory architecture, flexible sequential and random access memory fsram, is investigated for embedded systems
而我們開展的一項研究驗證了一種新型低功耗的片外存儲器結構的性能潛力，即靈活的順序與隨機存取存儲器lexible sequential and random access memory ，簡稱fsram 。 -
Vcma virtual channel memory architecture
虛擬通道內存結構 -
Vcma irtual channel memory architecture
虛擬通道內存結構 -
Uma unified memory architecture
統一內存架構 -
Sma : share memory architecture
共享內存結構 -
Sma share memory architecture
共享內存結構 -
Sm share memory architecture
共享內存結構 -
Smshare memory architecture
共享內存結構 -
X86 memory architecture
X86內存架構 -
Firstly, to improve the mpiformatdb ’ s speed, a novel parallel algorithm based on shared memory architecture is presented. by adding openmp directives, the cycled parallel structure is formed from the serial algorithm
為了提高mpiformatdb的性能，本文提出一種基於共享存儲結構的并行演算法，通過在原串列演算法中增加openmp編譯指導命令來構造循環級并行結構。 -
This dissertation refers to several typical examples of existing multipliers and accomplishes a specific multiplier, which can meet the performance requirement of t2181 processor. the designs of flexible power management, powerful serial ports and memory architecture are also included in this dissertation
乘累加器中的乘法器是影響系統性能的關鍵數據路徑，本文參考了現有的幾種典型乘法器結構，針對t2181dsp處理器的性能要求，提出了乘法器的改進結構，在此基礎上實現了高性能的乘累加器，為系統整體性能的提高奠定了基礎。
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