memory array 中文意思是什麼
memory array
解釋
存儲企列-
Fsmail adopts and implements the asynchronous event driven mechanism, with all those network i / o operations in the server working under the non - blocking style ; accomplishes object - oriented heap with the dynamic array, adapted to any type of data ; adopts the multi - queue scheduling mechanism based on a fsm, easily to fulfill the extentions of delivery funtions ; fulfills the non - blocking domain name resolvement mechanism and the caching of the resolved results ; implements the non - blocking user database management and the caching of the user data recently accessed ; uses the unified memory pool management, avoiding the memory leakage and improving the performance of the fsmail server ; lastly, implements the log management server based on the c / s mode, eliminating the inconsistency of the logging metadata and being adapted to any kind of application logging
Fsmail採用並實現了異步事件驅動機制，所有網路i o的實現使用了非阻塞方式；以動態數組實現了基於面向對象的堆隊列，屏蔽了堆數據的非一致性；使用了基於有限狀態機的多隊列郵件調度機制，為后續版本的擴展性提供了良好的介面機制；服務器內部實現了非阻塞的域名解析機制，並實現域名地址緩存；實現了非阻塞的用戶數據庫管理模塊，並實現用戶數據緩存；使用了統一的內存池管理機制，既防止了內存泄漏，又提高了服務器的性能；最後，還實現了基於c s模式的日誌管理服務器，屏蔽了日誌數據元的非一致性。 -
2 rayleigy and weibull distribution ground clutter for airborne phased array radar ( apar ) general pulse signal was simulate with method of zero memory nonlinear transform
二、利用零記憶非線性變換法實現機載相控陣雷達常規脈沖情況下的瑞利分佈、韋伯爾分佈的地面雜波模擬。 -
The following is main content of our thesis. the first, we analyze the system operation theory of cmos image sensor with pixel level adc ( a / d converter ). it is made up of three sections : pixel array, clock signal generator and sam ( sequential access memory )
本文的主要內容如下：首先，我們對像素級a d轉換型圖像傳感器的系統工作原理進行了分析，是由像素陣列、時鐘信號產生器和sam （順序讀寫存儲器）三部分構成的。 -
It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks
在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分，由於有了存儲器介面的存在，使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性，而只需關心傳輸協議和一些定義的遲滯參數，在客戶看來存儲器僅僅是一個線性的幀緩沖器，所有的換頁、區段切換都交由介面電路來處理，從而大大簡化了客戶對存儲器操作的復雜度。 -
The kanerva ' s sparse distributed memory ( sdm ) tackles the problem of training large data patterns and extendes the storage mode of existing computer. but it ' s address array produced randomly ca n ' t reveal the distribution of patterns and it has ' t the ability of function approximation for its learning rule
Kanerva的稀疏分佈存儲（ sdm ）模型解決了大維數樣本的訓練問題，推廣了現有計算機的存儲方式。但其地址矩陣的隨機預置方式不能反映樣本的分佈，並且sdm的學習方式使之不能用於函數逼近及時間序列預測問題。 -
A novel flash memory, which uses the source induced band - to - band tunneling hot electron ( sibe ) injection to perform programming, and a pmos selected divided bit - line nor ( pnor ) array architecture are originally introduced in this dissertation
本論文首次提出了一種採用源極誘導帶帶隧穿熱電子注入（ sourceinducedband - to - bandtunnelinghotelectroninjection ）進行編程操作的新型快閃存儲器技術和一種pmos選擇分裂位線nor （ pmosselecteddividedbit - linenor ）快閃存貯陣列結構。 -
An application exception represents the occurrence of a business logic error : withdrawing more than an account balance, reserving a seat which is already reserved, getting a credit card charge denied, etc. this is different from a system exception, which represents a system level error like running out of memory or running past the end of an array
應用程序異常表示發生了業務邏輯錯誤：取款超出了賬單余額、預訂已被訂出的座位、獲取已被凍結的信用卡的費用等等。這同系統異常不同，系統異常表示系統級別的錯誤，如耗盡內存或者數組越界。 -
The whole circuit includes memory array, decode, sense amplifier, data in - out circuit and pre - charge circuit
電路包括存儲陣列、譯碼電路、敏感放大器、數據輸入輸出電路，預充電電路等部分。 -
Cmos image sensor consists of image array logic registers, memory, timer pulse generator and converter
Cmos圖像傳感器包括圖像陣列邏輯寄存器、存儲器、定時脈沖發生器和轉換器在內的全部系統。 -
I had trained my dull memory to treasure up an endless array of soundings and crossing marks.
我還訓練了我那遲鈍的記憶力，使它能記住無數的測水記錄和橫渡標志。 -
Can free up memory by reducing the array size
可通過減小數組大小來釋放內存。 -
Used to release array variables and deallocate the memory used for their elements
用來釋放數組變量和解除分配用於它們的元素的內存。 -
On the base of analysis the specialty of distribute system, put forward memory the data with structure array, it is easiness to identify the structure of network and calculate
在分析配電網路特點的基礎上，提出採用結構數組存儲網路數據，便於識別網路結構和潮流計算，說明了識別網路結構的方法。 -
Some new technologies such as dividing the memory array into separated sub - arrays, atd, pre - charge and balance, subsection decoding, multilevel sense amplifier, etc have been used
設計中採用了諸如存儲陣列分塊技術，地址探測技術，預充電及平衡技術，分段譯碼技術，分級敏感放大器等一些新技術。 -
Suffix tree is a good index structure for smaller sequences, but it not suit large sequences, due to the so - called “ memory bottleneck ”. the suffix array is the closest competing structure, as it needs less space than a suffix tree. however, it is not convenient for searching
對于較小的序列來說，后綴樹索引無疑是一種很好的解決辦法，但由於它產生了「內存瓶頸」 ，不適合大的序列;后綴數組是另一種最具有競爭力的索引結構，與后綴樹相比，它需更少的存儲空間，但在數據搜索方面卻效率較低;基於q - gram和q - sample的索引方法雖然能用於快速搜索，但是不能用於搜索相似度低的數據。 -
A new memory array structure decreasing disturb between memory cells
一種減小存儲單元間串擾的新型陣列布局結構 -
Memory array redcode simulator
內存數組紅碼模擬器 -
Amorphous memory array
非晶存儲器陣列 -
A memory model describes the relationship between variables in a program instance fields, static fields, and array elements and the low - level details of storing them to and retrieving them from memory in a real computer system
內存模型描述的是程序中各變量（實例域、靜態域和數組元素）之間的關系，以及在實際計算機系統中將變量存儲到內存和從內存取出變量這樣的低層細節。 -
This paper presents an architecture based - on shift register array, which can be used for the search for the two search pattern simultaneously. this architecture was inspired by the vlsi architecture for diamond - search - pattern - based algorithms. it exploits the overlap of reference data among the search points to reduce data memory accesses which are the most power consuming operations
其基本思想是利用搜索點之間的參考數據重疊的特徵，把需要用於多個搜索點計算的參考數據存儲在移位寄存器陣列中，通過移位操作來滿足不同搜索點的計算需要，大大降低了數據存儲器訪問次數，從而減少了運動估計中功率消耗最大部分的操作。
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