parallel buffer 中文意思是什麼

parallel buffer 解釋
并行緩沖器
  • parallel : adj 1 平行的;并行的 (to; with); 【電學】並聯的。2 同一方向的,同一目的的。3 相同的,同樣的,相...
  • buffer : n 1 【機械工程】緩沖器,緩沖墊;阻尼器,減震器;消聲器。2 【化學】緩沖,緩沖劑。3 緩沖者;緩沖物...
  1. Involuntarily, questions of these engineering datas " management appear, datas " persistance only depending relational model and rdbms is greatly insufficient, so this paper carefully studies object - relational mapping based on rdbms based on the analyse of home & overseas actualities, correlative theories and realizing methods of object - relational mapping, we find opl based on rdbms is the most suitable for object relatinoal mapping of clera. based on the engineering application analyse of opl in clera, function requirements, database modes, interface criterions and functions, running modes of opl have being detailedly described. with the framework of microsoft dna, a kind of realizing method of opl based on com / dcom / activex component technology has being brought forward, and this paper describes realizing keys from base tables " definition, object id and class hx class and inheritance of class, object storage, parallel control and affair, object query, object nesting, relations between objects, support of complex data types, right control of object and buffer management of object

    本文在分析對象?關系映射技術的國內外現狀、相關理論及實現方法的基礎上,研究發現基於rdbms的opl是目前最適合clera的對象?關系映射方法;在clera的opl應用分析的基礎上,詳細描述了opl的功能要求、數據庫模式、介面規范與功能、運行方式等內容;結合microsoftdna開發框架,提出了一種基於com dcom activex組件技術的opl實現思路,並從基本表定義、對象標識與類標識、類與類繼承、對象存儲、並發控制與事務、對象查詢、對象嵌套、對象間聯系、復雜數據類型的支持、對象級權限控制及對象緩沖管理等幾方面概述了實現要點。
  2. Every column in sensor array work in parallel and have their own cds noise reducing circuit. the signals after fpn reducing are output from the output buffer amplifiers

    傳感陣列中各列感光單元的傳感信號并行輸出,分別由對應的相關二次采樣電路進行降噪處理,去除固定模式噪聲后的信號通過輸出緩沖放大電路進行輸出。
  3. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議( epp )與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上,給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計,其中,對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖,包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後,給出了測試結果,對研製工作做了總結,對本設計的優缺點各做了評述。
  4. The hardware designing include the interface with engine controller, such as d / a conversion. we chose the ad75089 which was produced by ad corp. this is a parallel port digital to analog conversion, and i give the presentation about its structure and connection scheme. in order to resolve the contradiction between faster computation and slower display, a buffer storage also needed

    第二部分詳細陳述了高速數據傳輸卡的軟、硬體設計過程,硬體設計包括dsp與pci總線的介面、 dsp與外部控制器的介面、以及電路卡上的擴展數據緩沖區的設計,並使用專門的工具軟體protel繪出全部硬體電路的設計原理圖。
  5. The framework generalizes the necessary steps of common radar processing, and solves the key problems of data registration, double - buffer storage, besides the data competition arbitration, and provides the ability of built - in parallel computation

    該程序框架概括了一般雷達處理流程的必要步驟,解決了數據注冊技術、雙緩存區存儲技術和數據競爭仲裁等關鍵技術問題,提供了內建的雷達并行處理能力。
  6. With the increasing of the number of parallel channels, the throughput of system can be improved and the transmission delay can be decreased. at the same time, the buffer of the receiver can be also reduced

    而且通過增加并行操作的子通道數,可以做到提高吞吐量,減少傳輸時延的作用,同時還能降低接收端對緩沖容量的要求。
  7. The series - parallel method is used to tune the parameter and the working set and buffer technology is adopted to boost the arithmetic efficiency

    在實現上,採用串并行相結合的學習方法對支持向量機參數進行調整,利用工作集和緩存技術提高學習演算法效率。
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