parallel distribution processing system 中文意思是什麼

parallel distribution processing system 解釋
并行頒布式處理系統
  • parallel : adj 1 平行的；并行的 （to; with）; 【電學】並聯的。2 同一方向的，同一目的的。3 相同的，同樣的，相...
  • distribution : n 1 分配，分發，配給；分配裝置[系統]；配給品；配給量；【經濟學】配給方法，配給過程；分紅；【法律...
  • system : n 1 體系，系統；分類法；組織；設備，裝置。2 方式；方法；作業方法。3 制度；主義。4 次序，規律。5 ...
  1. Chapter 4 studies scheduling algorithm of the core node to implement on single adsp2191. the result shows that a single adsp2191 chip can ’ t satisfy the bhp processing delay request and parallel processing is inevitable. chapter 5 primarily studies the core node ’ s scheduling algorithm with many dsp parallel process. details of lauc - vf scheduling algorithm analysis data flow organization and mission distribution are argued. the results of software simulation and hardware debugging indicate that many dsp parallel processing is effective and coincident with the system ’ s demand

    結果表明單片adsp2191晶元不能夠滿足核心節點對bhp的實時處理要求，必須多dsp并行處理。第五章研究了核心節點調度演算法的多dsp并行處理。對多bhp批調度演算法的實現進行分析，探討了多bhp處理任務的的劃分和分配方案;多dsp間數據通信和傳輸的dma實現;最後對多處理器并行的處理時間進行模擬測試分析。
  2. On the basis of summarization of the simulating technology of sonar signal, the paper brings forward the mathematics models of radiate noises of ships and torpedo, and simulates in computer ; tests the correctness of some pivotal methods through the simulation, on the basis of which, system scheme being brought out ; a parallel processor with twelve sharcs, combining with parallel processing theory and topographic configuration, is used to realize the algorithm of noise simulation on the basis of research on optimum distribution of algorithm and method of embedment in real time ; at last, gui, realized with vc + + language, is used to set parameters and control the whole parallel system flexibly and conveniently

    本文在綜述聲納信號模擬技術的基礎上，首先提出艦船和魚雷輻射噪聲的模擬數學模型，並進行了計算機模擬實現；通過計算機模擬驗證了一些關鍵技術的正確性，並由此提出系統實時實現方案；構造了一個12個處理器的并行處理機? sharc陣列，結合併行處理理論和sharc陣列的拓撲結構研究了有關模擬演算法的最優分配及其嵌入整個聲納系統的方法，實時實現了噪聲模擬演算法。最後，使用vc + +語言編寫人機界面，靈活、方便地進行參數設置以及對整個并行處理系統進行控制。
  3. In designing or selecting a topology for a parallel processing system, one fundamental consideration is system - level fault tolerance. in order to improve the fault tolerance, the paper analyses from the two following sides : one is by adding the less links related to the original networks, modifying the topology of the original one, we get higher fault tolerance of the new network ; the other is under the same topology network, ignoring the likelihood of one processor and ail its neighbors failing at the same time, or considering the distribution of the faulty nodes, that is studying the fault tolerance under the conditional connectivity or cluster - fault - lolerance

    本文以提高網路的容錯度為目的，從兩個方面分析互連網路的容錯性質：一是在原網路基礎上增加少量連接，使新型網路具有更高的連通度（容錯度為連通度減1 ） ；二是在給定互連網路拓撲結構下，考慮故障處理器發生的概率和故障處理器的分佈狀況，在其中的某一具體條件下，即在條件連通度和簇容錯下分析互連網路的容錯性能，從而得到更高的網路容錯度。
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