parasitic circuit 中文意思是什麼
parasitic circuit
解釋
寄生電路,寄生電流-
With soft - switching technology, inverter spot - welding power source has lower switching dissipation, lower electromagnetic interference and lower sensitivity to parasitic parameters of power circuit, contribute to inverter output characteristics and circuit efficiency, stability and reliability
採用軟開關技術的點焊逆變電源，可減小開關損耗、電磁干擾及對電路寄生參數的敏感性，並從根本上改善電路的輸出特性，提高電路的效率、穩定性和可靠性。 -
A lcc multi - resonant ( mr ) network is added to the traditional three - level converters to realize zvs. the unique arrangement of a multi - resonant network results in absorption of all major parasitic components hi the resonant circuit, such as transistor output capacitance, diode junction capacitance and transformer leakage inductance, which can eliminate parasitic oscillation in the converter
它的優點在於諧振電容吸收了開關管和續流二極體的結電容，諧振電感吸收了變壓器的漏感，使得開關管和續流二極體都能在軟開關的條件下完成導通和關斷過程，消除了電路中的寄生振蕩。 -
The mixed - signal flow should realize the communication between the digital circuit and analog one. it includes mixed - signal simulation, integration of the layout of digital and analog circuit, parasitic extraction and post - simulation
數模混合的設計流程要實現數模電路之間的信號通訊，它的主要流程包括：數字模擬電路的混合模擬，數字模擬電路版圖的整合和數字模擬電路提取寄生參數后的模擬。 -
Subsequently, we can get the chip s - parameter by adding the negative equipment circuit of the parasitic parameters in the s - parameter model of packaged device
之後，在有管殼封裝器件的s參數模型中，加上負的寄生參量的等效電路，即可得到管芯的s參數。 -
The accelerometer which has simple fabricated process and high sensitivity and small parasitic capacitance and residual stress is hybrid integrated with the interface circuit using ic nude chip. so the density of the package is increased, and the noise of the sensing system is decreased. these found the base of capacitive accelerometer module using the mcm method
該傳感器製作工藝簡單，靈敏度高，支撐梁採用u型，減小了刻蝕后的殘余應力，用玻璃作為襯底，減小了襯底和硅可動質量塊間的寄生電容，且把傳感器晶元和用ic裸片製作的介面電路集成在一起，提高了封裝密度，減小了傳感器系統的噪聲，為採用mcm技術製作電容式加速度傳感器模塊打下了基礎。 -
These rules are based on the extraction of all parasitic parameters of the layout and device modeling, including transition behavior, high frequency characteristics of the different materials, and electrostatic couplings to printed circuit board ( pcb ) conductors and to the ground
這些規則是基於抽取pcb的敷線和器件模型的所有寄生參數而建立的，寄生參數的抽取考慮到了瞬態行為，不同材料的高頻特性， pcb不同導體和各導體對地間的靜電耦合。 -
The macromodel is built up with the combination of device simulation and nonlinear curve fit, which makes the extraction of the substrate parasitic parameters more convenient and the circuit simulation more accurate
該宏模型通過器件模擬與非線性擬合相結合的方法建立，使襯底寄生參數的提取更加方便，同時保障了深亞微米電路特性的模擬精度。 -
With the software cadence, model establishment and parasitic parameter extraction are made on the main pcb lines of the proposed circuits. equivalent circuit models of common mode combined with differential mode current and noise simulation models are also established on full bridge switching - mode converters. study on the simulation of conducted interference noise is made with the software saber and the effects on the circuits " noise by the main parasitic parameters are also analyzed
在對全橋開關型變換器電路工作原理分析的基礎上，建立了全橋開關型變換器主要元器件的電磁干擾參數模型，利用cadence軟體對其pcb主要印製導線進行了建模分析和寄生參數的提取，得到了全橋開關型變換器傳導干擾的共模、差模噪聲電流等效電路模型以及噪聲模擬模型，並運用saber軟體進行了傳導性干擾噪聲的模擬研究，分析了主要寄生參數對電路噪聲的影響。 -
To put it into practice, the influences of the parasitic capacitances have to be further investigated using a simplified equivalent circuit
對于本課題組提出的反相共模抑制技術，使用一個簡化的等效電路，本文進一步研究了寄生電容在其中的影響。 -
In order to improve the circuit performance and reliability, the considerations of increasing influence of parasitic effects resulted from interconnect crosstalk and delay as well as the electromigration and power consumption drive the introduction of copper and low - k dielectric
為了提高電路性能及可靠性，並對連串擾及延遲引起的互連寄生效應影響的增長，電遷徙和功率損耗等方面進行綜合考慮，刺激了低電阻率銅和低介電常數介質的發展。 -
Design flow of analog circuit begins with drawing schematic and includes simulation, layout, drc / lvs check, parasitic extraction and post - simulation
模擬電路從schematic開始，其設計流程包括：模擬，版圖繪制， drc lvs檢查，寄生參數提取和后模擬。 -
In this paper, the soi technology is applied to the integrated circuit fabrication. soi technology overcomes some disadvantages of bulk silicon because of its inherent structure. it has the advantages such as no latch - up effect, low parasitic capacitance, high transconductance, simple structure, high density and good anti - radiation
Soi技術以其獨特的材料結構有效地克服了體硅材料的不足，它具有無閉鎖效應；漏源寄生電容小；較高的跨導和電流驅動能力；器件結構簡單；器件之間距離小；集成度高；抗輻射性能優良等優點。 -
The difficulty in design microstrip pin sp3t switch is the via hole for grounding. we use both the radial parts and the via hole to get a good result. the fin - line pin switch is fully simulated using full - wave analysis, the parasitic parameter and the circuit assemble need to be considered
微帶結構上過孔微波接地效果的不理想，是微帶單刀三擲開關的難點，本文採用了扇形的微波接地和過孔直流接地結合起來，較好的解決了這一問題。 -
To make use of parasitic parameter to design the circuit : because parasitic inductance induced by packaging could not only influence the circuit characteristics, but also lead to a design failure, the inductor value needed in the circuit can be designed in the amplifier according to the size of parasitic inductance
4 、利用寄生參數來設計電路。由於電路的封裝存在寄生電感，其不僅會影響電路的特性，而且可能造成電路設計工作的失敗，所以根據電路所需電感及其值的大小，將之有效的設計在放大器電路中。 -
The results that increasing of bias current and shunted resistance and lowing critical current and connected inductance can decrease the transmission time are shown ; ( 4 ) a new type of circuit, ladder shape multiplayer jtl. structure is provided by author, thus output signal of rsfq circuits can be amplified before transfer to room temperature electronics system. it has highly gain of amplify relatively and the double peak structure are avoided through decreasing parasitic capacitance
（ 4 ）針對目前超導與室溫介面電路的電壓放大器存在的「雙峰」和放大增益效率較低的不足，提出了一種全新的階梯式多層jtl電壓放大電路結構，較好的解決了以上的問題，通過初步的模擬分析證實，該電路的構思極負有創新性。 -
It has many advantages including excellent device isolation function, less parasitic effects among different parts, high speed, good radiation toleration, and high integration density, etc. consequently, high voltage soi spic has become a new field of power integrated circuit research
它具有器件隔離性能好、器件間的寄生效應小、電路工作速度高、抗輻射能力強和集成度高等優點。因此基於soi的高壓智能功率集成電路已經成為功率集成電路研究的新領域。 -
The design flow includes the construction of basic cell libraries, placing & routing, layout verification and post - layout simulation, etc. moreover, the layout design of basic cells and functional modules, the measures of circuit protection and methods to reduce the parasitic effect are also been discussed
這個流程介紹了與intelm80c287協處理器完全兼容的協處理器的後端設計過程。介紹了協處理器設計過程中基本單元和一些主要功能模塊的設計，以及設計中的保護措施和減少寄生效應的設計方法。 -
The parasitic effects of interconnect is the bottleneck of the entire circuit system performance
互連的傳輸線效應成為限制系統整體性能的「瓶頸」 。 -
We choose hb qrc convert as the research object. this paper has completely analyzed the circuit work modes, designed an experimental device, analyzed the mam noise source, established the common - mode and different - mode noise current models, extracted the parasitic elements of four pcb layout and simulated each emi level. based on these, it has derived the element which have great effect on pcb emc and has designed the optimized pcb layout
選擇一種半橋準諧振變換器作為研究對象，對其工作原理進行了詳細的分析，製作了實驗樣機，分析了它的主要干擾源，建立了它的共模、差模噪聲電流等效電路模型，對它的四種不同pcb布局進行了寄生參數提取和電磁兼容模擬，在此基礎上分析得到了影響其電磁噪聲水平的最重要因素，並設計出了最優的pcb布局。
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