parasitic process 中文意思是什麼
parasitic process
解釋
寄生過程-
With the development of electronic technology in the field of high - frequency and high - power, power mosfet is gradually enhancing its important status in semiconductor apparatus and is being widely applied in power converters as switch. with the increasing of the operating frequency ( > 200khz ), the energy loss caused by parasitic capacitance will affect the efficiency of power transforming in converters. especially in the applications of high frequency power supply using mosfet as main devices ( the unit of frequency is mhz ), the energy loss caused by the switch process will badly affect its efficiency
隨著電力電子技術進一步向高頻的大功率用電領域發展，功率mosfet在各種電力半導體器件中的重要地位日益顯著，使用功率mosfet作為開關器件的功率轉換電路也日益增多，但隨著器件開關頻率的提高（大於200khz ） ，由器件極間電容引起的能量損耗將會影響到功率轉換電路的能量傳輸效率，特別是在以mosfet作為開關器件的高頻感應加熱電源中（工作頻率可達兆赫） ， mosfet在開關過程中的能量損耗嚴重影響到電源的效率，因此如何減小開關器件的損耗提高高頻功率轉換線路的效率成為電力電子技術領域的重要研究課題之一。 -
The problem in high speed signal process, such as parasitic parameter and gate delay is also the difficulty hi the research
生成高速，穩定的時鐘信號是本課題的目標。高速信號處理所遇到的常見問題，如寄生參數，門電路延遲是設計難點。 -
Thus, it is believed that in subsequent high - temperature process, the base boron will outdiffuse very easily into emitter and collector, which will form a parasitic barrier for the electrons when moving from emitter into base and result in performance degradation of the device
這樣在後續的高溫工藝中就會引起基區的雜質外擴到集電區和發射區，產生電子勢壘，導致器件性能的嚴重退化。 -
The accelerometer which has simple fabricated process and high sensitivity and small parasitic capacitance and residual stress is hybrid integrated with the interface circuit using ic nude chip. so the density of the package is increased, and the noise of the sensing system is decreased. these found the base of capacitive accelerometer module using the mcm method
該傳感器製作工藝簡單，靈敏度高，支撐梁採用u型，減小了刻蝕后的殘余應力，用玻璃作為襯底，減小了襯底和硅可動質量塊間的寄生電容，且把傳感器晶元和用ic裸片製作的介面電路集成在一起，提高了封裝密度，減小了傳感器系統的噪聲，為採用mcm技術製作電容式加速度傳感器模塊打下了基礎。 -
It details the ic design process and vlsi circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays
它詳細規定了集成電路設計過程和超大規模集成電路電路，包括門陣列，可編程邏輯器件和陣列，寄生電容，及輸電線路的延誤。
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