phase lock detector 中文意思是什麼

phase lock detector 解釋
鎖相檢波器
  • phase : n 1 形勢,局面,狀態;階級。2 方面,側面。3 【天文學】(月等的)變相,盈虧;【物、天】相,周相,...
  • lock : n 1 鎖,閂,栓。2 (運河等的)船閘。3 制輪楔。4 【機械工程】氣閘,氣塞,鎖氣室。5 【軍事】槍機。6...
  • detector : n. 1. 發覺者。2. 偵查器。3. 【化學】檢定器。4. 【電學】檢電器。5. 【電訊】檢波器,指示器。
  1. The basic operation principle of phase - locked frequency synthesizer and the type of circuits are expatiated systematicly in this paper. the principle of operation on sampling phase detector and some characteristics including the linear tracking and phase noise in phase loop circuits are analyzed deeply. the research is emphased on the theory and design method of circuits in the sampling phase - locked frequency synthesizer. then, the expansion capturing circuit is analyzed and designed for better performance of capturing loop circuits. at last, the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling - holder. the general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product

    本文系統的闡述了鎖相頻率合成器的基本工作原理及電路類型;較深入地分析了取樣鑒相工作原理及電路、鎖相環路的線性跟蹤特性和相位噪聲特性;重點對取樣鎖相頻率合成器電路理論和設計方法進行了研究;為了改善環路的捕獲性能,對擴捕電路進行了分析和設計,並用wewb32軟體對電路進行了模擬;考慮到取樣保持器的附加相移影響,對環路濾波器進行了分析和設計。
  2. Then according to the emphasis of the design, went deeply into the theory of pll frequency synthesizers widely used, described pll ’ s working principle, structure and several types in detail, and made research and analysis of pll frequency synthesizers ’ phase noise, including the effect of the active loop filter on the phase noise, and give some methods to make improvement as well, such as changing loop filter form, reducing divide number, and increase phase detector frequency, etc. then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit, which are also important circuits in the design

    論文首先對幾十年頻率合成器的發展進行概述,而後針對本次設計的重點,對應用較為廣泛的鎖相頻率合成理論進行了深入的探討,詳細介紹了鎖相環的工作原理、組成結構和鎖相類型,並對鎖相頻率合成器的相噪特性進行了研究分析,包括有源環路濾波器對于相噪的影響,提出了改善相位噪聲的幾點措施:改善環路形式、降低分頻數、增大鑒相頻率等。接著介紹了直接數字頻率合成器( dds )和注入鎖相電路的原理特點以及相噪分析,它們也是本次設計的重要電路。
  3. First, an analysis for the design of the impulse phase lock oscillate, which includes impulse phase detector the dielectric resonant oscillate etc. secondly, presents an analysis for the design of wide band balanced low noise amplifier. the last two part simplify the theory and the electrical characteristics of the sub harmonic mixer, and the mmvco

    第一部分著重介紹了脈沖鎖相源的工作原理(主要包括取樣鑒相器和介質穩頻的壓控振蕩器) ,並介紹了研製結果的性能指標;第二部分介紹了平衡式寬帶低噪聲放大器的基本理論
  4. The main contribution of the thesis is seen as follows : aiming at the fault with slow speed and high power dissipation of the conventional phase - frequency detector, a high speed and low power dissipation phase - frequency detector is designed by modifying the structure of the single phase lock dynamic d flip - flop and adding the delay cell in the feedback loop to eliminate the phase detector ’ s dead zone effectively

    論文的主要貢獻為以下幾個方面: 1 .針對傳統鑒頻鑒相器速度慢、功耗高的缺點,改進了單相時鐘動態d觸發器的結構,設計出了一種高速低功耗的鑒頻鑒相器,在反饋迴路上加入延遲單元,能有效的消除鑒相死區。
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