phase-locked loop 中文意思是什麼

phase-locked loop 解釋
鎖相環路
  • phase : n 1 形勢,局面,狀態;階級。2 方面,側面。3 【天文學】(月等的)變相,盈虧;【物、天】相,周相,...
  • locked : 閉塞的
  • loop : n 1 (用線、帶等打成的)圈,環,匝,框,環孔,線圈;【醫學】(常 the loop)宮內避孕環。2 環狀物,...
  1. Chapter 3 discusses the modules used in the fh - mpsk and fh - / 4dqpsk systems. these modules include : duc / ddc ( digital up converter / digital down converter ), nyquist flitter, burst start detection, interpolation module, pll ( phase locked loop ), pll error extraction, initial phase correction and the coding and decoding for tcm

    第三章主要討論了跳頻模式下fh - mpsk和fh - 4dqpsk系統中各個模塊的設計,這些模塊包括:上下變頻器、奈奎斯特濾波器、信號到達檢測、插值模塊、通用環路、各環路誤差提取方法、初始相位校正和tcm編譯碼。
  2. This paper illuminates theory, structure, spectrum distribution, merits and defects, especially spurs of direct digital synthesis ( dds ), and it then introduces phase locked loop ( pll ) theory

    對dds的結構、優缺點、頻譜分佈,特別是雜散性能進行了詳細的闡述。接著,又介紹了鎖相環( pll )的原理。
  3. The carrier wave is modulated directly by the baseband signal at several frequency point in l band and s band. firstly, this paper clarifies the theory of i / q modulation, elaborates evm and acpl, and analyzes the effect of amplitude and phase unbalance and dc offset on evm. secondly we review the basic principle of phase locked loop and it ’ s composing parts, including the basic conception and design method of pll frequency synthesizer, especially introduce the charge pump pll frequency synthesizer in detail

    首先,在闡述i / q正交調制基本原理的基礎上,通過對誤差矢量和鄰近通道功率泄漏的詳細分析,定性、定量地討論了各種非理想電路因素(如相位不平衡、幅度不平衡、直流偏差等)對調制器性能的影響;其次,介紹了鎖相環的工作原理和基本組成部分,包括鎖相環的設計和環路濾波器的設計,特別詳述了電荷泵鎖相頻率源;第三,介紹了採用直接調制技術模擬衛星信號的射頻前端的設計;最後,對整個直接射頻調制系統進行測試,結果基本上達到了課題要求。
  4. Because massive harmonic interference in the electrical network, it causes signal - sampling to include the very big harmonic in the measurement system, for eliminating measurement result influence by harmonic, the paper has an in - depth study of fourier transformation harmonics analysis measurement principle, analysis the forming reasons of frequency spectrum leakage and railing effect during measurement, achieves phase locked loop and frequency multiplier technique to realize integer - period synchronous sampling and eliminate impact of frequency spectrum leakage and railing effect in the result of measurement, and investigates in depth theory on phase locked loop and frequency multiplier technique, gives the method of realizing phase locked loop and frequency multiplier technique

    由於電網中存在大量的諧波干擾,導致測量系統中取樣信號也含有很大的諧波,為了消除諧波對測量結果的影響,論文深入研究了傅立葉變換諧波分析法的測量原理,分析了測量中頻譜泄漏和柵欄效應形成的原因,提出了採用鎖相環倍頻技術實現信號的整周期同步采樣,消除頻譜泄漏和柵欄效應對測量結果的影響,並對鎖相環倍頻技術的理論進行了深入研究,給出鎖相環倍頻技術的實現方法。
  5. A multi - layer charge - pump phase - locked loop behavioral model

    一種電荷泵鎖相環的多層行為級模型
  6. 3. with comprehensive improvement of transponder including structural adjustment to lna ; optimization of ( phase locked loop ) pll filter ; structural adjustment to the transmitter and phase error adjustment to the intermediate frequency demodulation circuit, we have successfully enhanced sensitivity, expanded dynamic range, increased transmitting power and improved the spectrum purity ; decreased capture time for pll ; improved the signal quality after demodulation ; reduced its volume and power consumption. 4

    3 、對通信機的全面改進,包括lna結構的調整、鎖相環環路濾波器的優化、發射部分結構的調整以及中頻解調電路的相差調整,提高了系統的接收靈敏度、改善了本振的頻譜純度、減少了鎖相環的鎖定時間、使中頻解調后的信號質量大為提高,同時還減少了體積、節約了系統的功耗。
  7. An application of lmx2306 in the frequency synthesizer based on the phase - locked loop

    超高頻接收機中鎖相環的設計
  8. Since commercial pll ic came out, phase - locked - loop frequency synthesis has become widely accepted. but when narrow frequency - step is required, the loop bandwidth has to decrease while cannot meet the demand of frequency - hopping speed

    數字鎖相集成器件出現以來,鎖相式頻率合成器得到迅速發展,但是當需要窄頻率步進時,環路帶寬需要降低,致使鎖定時間變長,不能滿足快速跳頻的要求。
  9. It has been an important component of communication, radar, instrument, high - speed computer and navigation equipment. fractional - n phase locked loop ( fnpll ) frequency synthesis has been appeared in recent years

    頻率合成器是一種相位鎖定裝置,是通訊、雷達、儀器儀表、高速計算機和導航設備中的一個重要組成部分。
  10. A phase - locked - loop - based model reference adaptive system for speed estimation of sensorless induction motor drives

    一種基於鎖相環原理的參考模型自適應感應電機轉速估計方法
  11. In this thesis, phase - locked loop ( pll ) technogies are used to acquire phase of fundamental current in bais current, which enhances the detecting precision of bais current. and we want the phase of bais current and the phase of system current is the same, so this thesis think of locking the phase of bais current which based on this theory to sure the security and the reliability of apf

    本文採用鎖相技術,以獲得畸變電流中基波電流的相位,進一步提高了畸變電流的檢測精度,並據此原理考慮鎖定補償電流的相位,使補償電流與系統電流相位同步,保證apf安全可靠運行。
  12. For keeping the frequency and phase synchronous to the grid, a pll ( phase locked loop ) is necessary

    為了使並網電流和電網電壓同頻、同相,需要使用鎖相環技術。
  13. Implementation of fpga based three phase phase - locked loop system

    的三相鎖相環實現
  14. The method of picking up synchronizated signal is digital phase - locked loop, which is picking up phase information from the suddenly toggle between codes

    提取碼同步信號一般採用鎖相環技術,利用碼元間存在的瞬間跳變獲取需要的相位信息。
  15. The principal of the digital communication theory and the relational theory of the synchronization are introduced in fourth chapter. in fifth chapter, author detailedly describes the methods of two kind digital phase - locked loop, expounds the processing of design and implementation by fpga

    第四章介紹了數字通信中位同步的相關理論,並在第五章詳細敘述了兩種數字鎖相位同步的原理,並論述了使用fpga設計實現這兩種位同步方法的過程。
  16. The principle and structure of pll ( phase - locked loop ), including fll and loop filter, are analyzed and described. the module of carrier synchronization in the all - digit ds - qpsk receiver was carried out in the fpga chip. the problem about the estimation and track of the correlative carrier frequency under high dynamic circumstances was resolved very well

    針對某遙測遙控全數字接收機的研製,對相干載波同步中的鎖相環、鎖頻環、 dpll 、本地nco等進行了詳細的分析和優化設計,在fpga上實現了高動態全數字ds - qpsk接收機中的載波同步模塊,解決了大范圍和動態多普勒頻移下接收機的相干載波提取與跟蹤問題。
  17. It has the advantage of high frequency resolution and low phase noise when compared with traditional integer - n phase locked loop ( npll ) frequency synthesis

    分數分頻( fnpll )頻率合成器則是近年來出現的一種新技術,它與傳統的整數分頻頻率合成器相比具有頻率解析度高、相位噪聲低等優點。
  18. Phase locked loop technique offers a way to resolve this problem

    鎖相式頻率合成技術提供了解決這一問題的思路。
  19. In addition, this paper analyzes the noise - filtering quality of phase locked loop, a / d transformation theory, and the combination and quality of the decimation filter

    並對鎖相環對噪聲的過濾性能、 a / d轉換原理和抽取濾波的組成及性能進行了深入地分析。
  20. The paper, for the harmonics detection method used in power system, presents an sampling method based on frequency multiplication phase - locked. through phase - locked loop to track the power wave, which not only reduces the affect of spectrum leakage to the harmonics analysis, but also realizes quick. accurate and, real - time measurement

    本論文主要針對電力系統中採用的諧波測量方法而提出的一種基於鎖相倍頻採集方法,通過鎖相環對電力波形進行實時跟蹤,既解決了頻譜泄漏對諧波測量精度的影響,又實現了快速的,準確的,實時性的測量。
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