pipeline stage 中文意思是什麼
pipeline stage
解釋
流水線站-
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too
詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。 -
The accidents most occurred in the early stage and the later stage after these pipelines was brought into use, especially the late stage, the possibility of accidents increases greatly with the increment of pipeline ' s service time, most pipelines in our country have been brought into service for more than 20 years, and all entered in the dangerous period, so efficient techniques must be developed to farthest reduce the possibility of accidents
管道投入運行的早期和後期是事故的高發期，特別是服務後期，管道事故發生的可能性隨著服務期限的增加急劇增加，而我國多數管道服務都已有20多年了，到了事故高發期，必須盡快採取有效措施，最大限度地減少事故的發生。 -
Three precautionary measures to prevent natural gas hydrates in pipe from blocking are put forward, that is, not to used bending pipe if possible during construction stage ; increasing pigging frequency before pipeline commissioning to elimninate water within pipe ; injecting inhibitor in regular way
提出了三項預防水化物的措施：施工階段避免過多使用彎管；投產前增加吹掃次數，徹底清除水；運行初期定期注入抑制劑。 -
Design of 3 - stage instruction pipeline 51 core
一種採用3級指令流水線的51內核設計 -
Two - stage adaptive noise cancellation algorithm for ultrasonic test of oil pipeline
石油管道超聲檢測信號的兩級自適應噪聲消除演算法 -
The functional descriptions of these error mechanisms which can reveal how errors of various blocks in adc affect the output sample are provided ; analyses show that the first stage of the converter is dominant in a pipeline
首先，通過研究流水線采樣保持電路、子adc 、子dac和殘差放大級的主要誤差機制，用函數表達式將誤差等效到采樣輸出端，量化各部分誤差對系統性能的影響。 -
The system - controlled iir filter and fft were realized using fpga in this paper, and modified pipeline structure is adopted to greatly raise the running speed in the system - controlled iir filter. in the same time, it is used that the algorithm of n - point complex to compute 2n - point real data block in the radix - 2 fft. it is different to the normal method in the adoption of pipeline single dual ram for each stage
論文用fpga實現了系統的受控iir濾波器和fft部分，受控濾波器採用改進的流水線結構，運行速度得到了大幅度的提高，同時運用n點復數dft演算法來計算2n點實數數據，在fpga中實現了基2的1024點復數fft ，同一般的實現不同，採用了流水線式的每級單個雙口ram的方法，節省了ram的容量，經驗證，該設計符合濾波器系統的要求。 -
Application of two - stage self - adapting filter method in magnetic flux leakage ndt of oil pipeline
兩級自適應濾波在輸油管道漏磁檢測中的應用 -
As a important component in cppm - gis, this paper illustrates detailedly the mathematics model of optimum design and direct optimization method for drainage pipe - net under gis. as a key stage in planning and designing the drainage system, the caculation of pipe - net is very critical and time - consuming. this paper brings forward the recursive arithmetic for pipe - net and pipeline designed - discharge
在cppm - gis系統中，水力計算模塊是一個重要的組成部分。本文詳細論述了gis環境下建立排水管網優化設計的數學模型、排水管網的直接優化法。 -
It is a risc microprocessor, has a six - stage pipeline, with separated data cache and instruction cache
銀河ts - 1採用典型的risc結構，六級流水線，具有獨立的指令cache和數據cache 。 -
Under 0. 35um si - cmos process, considering the trade off of accuracy and speed in the adc, 2. 5 - bit were converted in the first stage of the pipeline. using the improved calibration scheme and full difference structure and bottom - plant sampling technique to reduce the errors of the 10 - bit ( 2. 5 + 1. 5 5 + 3 ), 100msample / s pipeline adc
在0 . 35 m工藝水平下，通過折衷考慮提高系統線性度和降低功耗的要求，將流水線第一級精度取為2 . 5位，採用改進的冗餘位演算法，並結合全差分結構，下底板采樣等技術對一個（ 2 . 5 + 1 . 5 5 + 3 ）結構的10位100msample / s流水線adc系統進行校正。 -
The goal of this compensation scheme is to make the adc tolerant of comparator offsets and can detect input signals ’ overflow and achieve the desired linearity 。 dominant error mechanisms in the s / h, sub - adc, sub - dac and gain stage are defined and characterized for an arbitrary stage in the pipeline
基於對流水線工作原理和誤差機制的深入研究，提出了一種適用於10位100msample / s流水線adc的新型冗餘校正技術。該技術目的在於校正比較器的失調，實現溢出判斷功能，以提高系統線性度。 -
The or1200 is a 32 - bit scalar risc with harvard microarchitecture, 5 stage integer pipeline, virtual memory support ( mmu ) and basic dsp capabilities
Or1200是一種32位、標量、哈佛微體系結構、 5級整數流水線risc ，支持虛擬存儲器和基本的dsp功能。 -
Using pipeline technique to accomplish the most important operation in more than one stage, such as sad, which could not be finish in one pipeline stage at any cost. the on - chip memories and data path usually consume most percentage of power in media processor chip
數據通路的功耗也是dsp處理器功耗的重要部分，考慮採用門控時鐘技術防止mac模塊和alu模塊同時工作造成的功耗浪費，最後分析了md32晶元的功耗特徵。 -
This processor processes 9 - stage pipeline, and risc instruction set. its operation frequency is capable of achieving over 150mhz
該數字信號處理器的cpu具有先進的vliw結構內核、九級流水線，具有類似risc的指令集，它的工作頻率可達到150mhz以上。 -
According to the task and delay information of the floating - point unit, it was implemented with three - stage pipeline, including pre - normalization stage, calculation stage and post - normalization stage. approximately, the delay of each stage is equal with each other. also, floating - addition, floating - subtraction and floating - multiplication can been implemented by the floating - point unit
根據浮點單元承擔的任務及延遲信息，採用三級流線實現：前規格化級（ pre - normalizationstage ） 、計算級（ calculationstage ） 、后規格化級（ post - normalizationstage ） ，每一級的工作量和延遲近似相等。
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