pipelined system 中文意思是什麼
pipelined system
解釋
流水線系統-
Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail
基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。 -
Moreover, regulating the signals from the sub - detectors of besiii is the key technique that could determinates whether trigger system discriminates the good events. this paper describes a pipelined digital programmable delay module, which is to be used in the global trigger, designed as a single width 6u standard vme module. two main method are used in the preliminary design : one utilizes shit register and multiplexers, which is simple and reliable
在預研製過程中，使用了兩種可編程的延遲方法並對比了這兩種方法：一種是利用移位寄存器與多路選擇器串聯來實現可編程的延遲，此方法簡單、可靠性強；另一種則是利用雙口ram具有的獨立的讀和寫地址線，在設計中使讀、寫地址間距可調來實現可編程延遲。 -
Design and implementation of a fast round robin scheduler, in which a pipelined barrel shifter and a pipelined priority encoder are used ; testbench development of functional simulation for module verification and system verification, in which the bfm simulation model are used and some reference examples are proposed ; discussing the questions that should be paid attention to when using fpga to design high speed circuits and some design skills ; taking part in the system ' s integration and fpga implementation ; taking part in the system ' s test and verification ; the design of this thesis has provided some key method for inter - communication among different network processors, and also accelerated the development of communication products
討論了用fpga設計高速電路應注意的問題和一些常用的設計技巧；參與整個轉換邏輯的系統集成和fpga實現；參與系統的驗證工作；通信協議轉換邏輯的設計不僅可以解決不同網路處理器之間互通的問題，而且對于促進國產數據通信產品的研究與開發具有很重要的意義。同時在設計的過程中，進一步地探討了基於fpga的高速電路設計技術，對于fpga的設計有參考價值。
分享友人