pll (phase-locked loop) 中文意思是什麼

pll (phase-locked loop) 解釋
鎖相環路
  • pll : 多聚l-賴氨酸
  • phase : n 1 形勢，局面，狀態；階級。2 方面，側面。3 【天文學】（月等的）變相，盈虧；【物、天】相，周相，...
  • locked : 閉塞的
  • loop : n 1 （用線、帶等打成的）圈，環，匝，框，環孔，線圈；【醫學】（常 the loop）宮內避孕環。2 環狀物，...
  1. Chapter 3 discusses the modules used in the fh - mpsk and fh - / 4dqpsk systems. these modules include : duc / ddc ( digital up converter / digital down converter ), nyquist flitter, burst start detection, interpolation module, pll ( phase locked loop ), pll error extraction, initial phase correction and the coding and decoding for tcm

    第三章主要討論了跳頻模式下fh - mpsk和fh - 4dqpsk系統中各個模塊的設計，這些模塊包括：上下變頻器、奈奎斯特濾波器、信號到達檢測、插值模塊、通用環路、各環路誤差提取方法、初始相位校正和tcm編譯碼。
  2. Pll - qpsk, phased - locked loop quadrature phase shift keying

    鎖相環四相相移鍵控
  3. This paper illuminates theory, structure, spectrum distribution, merits and defects, especially spurs of direct digital synthesis ( dds ), and it then introduces phase locked loop ( pll ) theory

    對dds的結構、優缺點、頻譜分佈，特別是雜散性能進行了詳細的闡述。接著，又介紹了鎖相環（ pll ）的原理。
  4. The carrier wave is modulated directly by the baseband signal at several frequency point in l band and s band. firstly, this paper clarifies the theory of i / q modulation, elaborates evm and acpl, and analyzes the effect of amplitude and phase unbalance and dc offset on evm. secondly we review the basic principle of phase locked loop and it s composing parts, including the basic conception and design method of pll frequency synthesizer, especially introduce the charge pump pll frequency synthesizer in detail

    首先，在闡述i / q正交調制基本原理的基礎上，通過對誤差矢量和鄰近通道功率泄漏的詳細分析，定性、定量地討論了各種非理想電路因素（如相位不平衡、幅度不平衡、直流偏差等）對調制器性能的影響;其次，介紹了鎖相環的工作原理和基本組成部分，包括鎖相環的設計和環路濾波器的設計，特別詳述了電荷泵鎖相頻率源;第三，介紹了採用直接調制技術模擬衛星信號的射頻前端的設計;最後，對整個直接射頻調制系統進行測試，結果基本上達到了課題要求。
  5. 3. with comprehensive improvement of transponder including structural adjustment to lna ; optimization of ( phase locked loop ) pll filter ; structural adjustment to the transmitter and phase error adjustment to the intermediate frequency demodulation circuit, we have successfully enhanced sensitivity, expanded dynamic range, increased transmitting power and improved the spectrum purity ; decreased capture time for pll ; improved the signal quality after demodulation ; reduced its volume and power consumption. 4

    3 、對通信機的全面改進，包括lna結構的調整、鎖相環環路濾波器的優化、發射部分結構的調整以及中頻解調電路的相差調整，提高了系統的接收靈敏度、改善了本振的頻譜純度、減少了鎖相環的鎖定時間、使中頻解調后的信號質量大為提高，同時還減少了體積、節約了系統的功耗。
  6. Since commercial pll ic came out, phase - locked - loop frequency synthesis has become widely accepted. but when narrow frequency - step is required, the loop bandwidth has to decrease while cannot meet the demand of frequency - hopping speed

    數字鎖相集成器件出現以來，鎖相式頻率合成器得到迅速發展，但是當需要窄頻率步進時，環路帶寬需要降低，致使鎖定時間變長，不能滿足快速跳頻的要求。
  7. In this thesis, phase - locked loop ( pll ) technogies are used to acquire phase of fundamental current in bais current, which enhances the detecting precision of bais current. and we want the phase of bais current and the phase of system current is the same, so this thesis think of locking the phase of bais current which based on this theory to sure the security and the reliability of apf

    本文採用鎖相技術，以獲得畸變電流中基波電流的相位，進一步提高了畸變電流的檢測精度，並據此原理考慮鎖定補償電流的相位，使補償電流與系統電流相位同步，保證apf安全可靠運行。
  8. For keeping the frequency and phase synchronous to the grid, a pll ( phase locked loop ) is necessary

    為了使並網電流和電網電壓同頻、同相，需要使用鎖相環技術。
  9. The principle and structure of pll ( phase - locked loop ), including fll and loop filter, are analyzed and described. the module of carrier synchronization in the all - digit ds - qpsk receiver was carried out in the fpga chip. the problem about the estimation and track of the correlative carrier frequency under high dynamic circumstances was resolved very well

    針對某遙測遙控全數字接收機的研製，對相干載波同步中的鎖相環、鎖頻環、 dpll 、本地nco等進行了詳細的分析和優化設計，在fpga上實現了高動態全數字ds - qpsk接收機中的載波同步模塊，解決了大范圍和動態多普勒頻移下接收機的相干載波提取與跟蹤問題。
  10. The phase noise in microwave receiver and the measured parameter of source frequency instability are described in this paper, and the technology of frequency - synthesizing and theory of phase locked loop ( pll ) are also briefly introduced

    摘要闡述了微波接收機中的相位噪聲概念及本振源頻率不穩定度的實際測量參數，並簡要介紹了頻率合成技術和鎖相環路工作原理。
  11. This paper introduces the principle of phase - locked loop and analyzes the performance characteristics of pll chip adf4106 which has wide bandwidth and low power consumption. and then introduces the design method of a kind of low phase noise frequency synthesizers which uses single chip processor to control the chip. the application supplies a good design method for high frequency synthesizer

    介紹了鎖相環路的工作原理，分析了低功耗寬帶集成鎖相環晶元adf4106的工作特性，並介紹了一種利用單片機控制該晶元的低相位噪聲頻率合成器的設計方法，討論了環路濾波器的設計，為高頻頻率合成器的設計提供了很好的思路。
  12. Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop ( pll )

    然後介紹了鎖相環（ pll ）的基本結構、相位模型、頻率響應、噪聲及雜散性能。
  13. The task of carrier synchronization is tracking the frequency and phase of a carrier wave, the most effective means for tracking small frequency deviation and the phase of a carrier is using the phase - locked loop ( pll )

    載波同步的任務就是跟蹤載波的頻率和相位，對于載波相位及小頻偏的跟蹤，最有效的方式是使用鎖相環。
  14. Chapter 2 discusses the modulation and demodulation theory and the principle of pll ( phase locked loop ) from the general communication theory to several modern modulation techniques

    從通信傳輸的一般原理到幾種具體的現代調制技術，並針對dvb - s接收晶元簡要敘述了qpsk的解調原理。
  15. Pll phase locked loop

    鎖相迴路
  16. In chapter 1, the basic principle and structure of the integrated anti - interference data transmission system are introduced. in chapter 2, the theory of maximum likelihood ( ml ) carrier synchronization parameter estimation ( frequency estimation and phase estimation ) are expatiated, and the closed - loop recovery methods ( phase - locked loop, pll ) and some other arithmetic in common use are introduced

    第二章對最大似然（ ml ）載波同步參數估計（頻率估計和相位估計）理論進行了闡述，對常用的閉環恢復法即鎖相環（ pll ）法和一些載波同步參數處理方法進行了介紹，並對常用的載波頻率估計方法作了分析比較。
  17. On basic of researching the principle of phase locked loop, this article analyzes the output signal whose noise characteristics depend on the each part of pll, and designs a scheme to realize the frequency synthesizers using the high performance chips with integrated prescalers and phase detectors. the visualized circuit structure is given in this paper

    本文在研究鎖相環路基本原理的基礎上，分析了鎖相式頻率合成器電路中各部件對環路輸出信號噪聲性能的影響，設計了以一個高性能的集成鎖相環頻率合成器晶元為基礎實現頻率合成的方案，並給出了具體的電路形式。
  18. Sigma delta modulation frequency synthesis is an advanced technology that applies in pll ( phase - locked loop ) frequency synthesizer, which could transform the spurs created by fractional - n synthesizers into phase noise that could be filtered by inherent low - pass identity in pll

    此技術應用-調制將鎖相環頻率合成器中分數分頻器產生的相位雜散轉化為相位噪聲，通過鎖相環本身低通濾波特性濾除，從而使用單環即可獲得很高頻率解析度和極低的相位雜散。
  19. A signal - generated scheme that is used in high solution ac source is presented based on the reasonable usage of system source. by discussing the methods of counter - output, pll ( phase - locked loop ) - output and dds ( direct digital synthesization ) - output, dds - based dummy - space method is brought out and it converts the time problem into space, improves the resolution of both frequency and phase - shift

    通過對計數器輸出法、基於鎖相環單片機合成及基於dds （ directdigitalsynthesization ）的單片機合成幾種方法的討論，引出一種基於dds的虛擬空間法，將時間上所面臨的問題轉化到內存空間上進行處理，極大地提高了交流電源的調頻、移相精度。
  20. On the promise of holding the control means of pll, introducing the control ways of wnn optimized by immune algorithms into the control of induction heating power, the author brought forward a multiple control strategies, that is, combined a wave neural networks which optimized by means of immune algorithms with digital phase locked loop circuit. simulation results show that it is feasible and effective

    在保留鎖相環控制的基礎上，引入了基於免疫優化的小波神經網路，提出了把小波網路控制和數字鎖相環控制相結合的控制策略，並以感應加熱電源為控制對象，模擬結果表明了該控制策略的有效性與可行性。
分享友人
分享到 Line

分享到臉書