processor data bus 中文意思是什麼

processor data bus 解釋
處理機數據總線
  • processor : n. 1. 〈美國〉農產品加工者;進行初步分類的人。2. (數據等的)分理者;【自動化】信息處理機。
  • data : n 1 資料,材料〈此詞系 datum 的復數。但 datum 罕用,一般即以 data 作為集合詞,在口語中往往用單數...
  • bus : n (pl busses buses)1 公共馬車;公共汽車;客機。2 〈口語〉汽車,機器腳踏車;飛機。3 【電學】信息...
  1. Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method

    在本設計中,採用高速的dsp處理器,實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法,實現了大電流信號的驅動輸出;採用485總線技術,組建了裝置主機與多探測器之間的主從式通訊網路,實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路,採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術,實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元,設計了人機信息交互的介面;採用了模塊化的軟體設計方法,開發了裝置主機及探測器的軟體程序。
  2. Tms320vc5402 is a fixed - point digital signal processor, made by texas instruments incorporated, which is 16 - bit word length. vc5402 has enhanced harvard architecture built around one program bus, three data buses, and four address buses for increased performance and versatility

    另外,採用mcs - 51系列cpu作為採集處理卡板載mcu也存在一些比較嚴重的問題,如cpu的指令執行速度慢,總線帶寬窄等缺點,不能完成數據的高速處理。
  3. Measure and control unit adopted 16 - bit, high - speed a / d converter, it can guarantee the speed and precision of alternating sample. the part of communication adopted can bus to transmit the data, it was suitable for real - time control and can guarantee dependability. it adopted the can bus adapter of yan - hua company whose type was pcl - 841 to communicate with processor unit the processor unit adopted industrial pc, which can guarantee the system work well for a long time

    其中下位裝置採用西門子公司的高性能十六位處理器c167cr - lm ,其內嵌can總線控制器便於通過can總線與上位機進行通訊,數據採集部分採用十六位高速a d轉換器從而保證了交流采樣的速度與精度,通訊部分採用可靠性高,適于現場實時控制的can總線來傳輸數據,與上位機介面採用研華公司的型號為pcl - 841的can總線適配器,為保證系統長時間可靠運行上位機採用工控機。
  4. The features of pci local bus, signal definition, command definition, bus operation and the addendum of the pci local bus specification, revision2. 3 are introduced briefly at first. then the structure and function of plx pci 9656 pci bus mastering i / o accelerator are summarized including : pci 9656 ' s three data transfer modes ( direct master, direct slave, and dma ) and direct connection to three processor local bus types ( m mode, c mode. j mode )

    在簡要介紹了pci總線的特點、 pci總線的信號、命令和操作規范、 pci總線的配置空間以及有關最新pci總線規范pci2 . 3里的一些新增和修改的內容之後,本文概述了plx公司的pci總線專用控制器pci9656結構和功能,並介紹了pci9656的發起者、從設備、 dma三種工作模式以及m 、 c 、 j三種局部總線介面方式。
  5. This scheme fully considers the internal structure of jx5 microprocessor, at the same time, the processor ’ s processing ability, address and data bus architecture is efficiently utilized. so with the minimal testing cost, a strong fault testing and trace debugging ability is provided to meet the jx5 processor ‘ s testing demand

    該方案充分考慮了jx5的內部結構,有針對性的選擇了一系列成熟可靠的可測性技術和方法,經過精心組合搭配,並充分利用jx5所具有的處理能力和cpu特有的地址、數據總線結構,在盡量少的增加測試開銷的前提下,提供了很強的故障測試和追蹤調試能力,很好的滿足了jx5對測試的需求。
  6. Then, chapter four describes the details of the implementation of video processing subsystem from processor unit, storage architecture unit, data i / o host - slave bus, data i / o interconnection unit four design aspects. in chapter five, host application programs and windows device driver design based on wdm are discussed

    第四章從處理器單元設計、存儲結構單元設計、數據i o主從總線設計,數據i o互連總線設計和系統控制中心單元設計五個方面分析視頻處理子系統的詳細設計。
  7. And a faster processor is useless unless the memory and bus architecture allows pcs to deliver data to the processor more efficiently

    除非存儲器和總線的體系結構使pc機能更有效地向處理器輸送數據,否則速度更快的處理器也沒有用。
分享友人