processor level 中文意思是什麼
processor level
解釋
處理機級-
With the development of the network and the multi - processor system, the research, simulation and the impemeni of the system - level fault diagnosis which is the very important means to increase the reliability of the system, are becoming more and more important. on the system - leve1 fault diagnosis, based on the group theory of system - level fault diagnosis that has been put forward by pro f zhang, the paper constructs newly the theory bases, improves on the matrix method, reinforces and consummates group arithmetic of all kinds of test mode, for the first time, analyses and discusses the equation solution of all kinds of models, so al1 the consistent fault patterns ( cfp ) could be found, straightly and high efficiently, even if the sufficient and necessary condition of t - diagnosable is dissatisfied and the complexity of system - level fault diagnosis is greatly decreased, especialy in strong t - diagnosabl6 system. last the simulation system ' s function has been extended and the application hotspot and the development trend have been disscussed
本人在張大方教授等人提出的基於集團的系統級故障診斷的理論基礎上，重新構建了系統級故障診斷的理論基礎，定義了系統級故障診斷測試模型的三值表示；改進了系統級故障診斷的矩陣方法，重新定義了測試矩陣、鄰接矩陣、結點對、結點對的相連運算、極大準集團和斜加矩陣，由此能直觀、簡便地生成集團和極大獨立點集；補充和完善了各類測試模型的系統級故障診斷的集團演算法，通過定義集團測試邊和絕對故障集，簡化了集團診斷圖，由此能較易地找到所有的相容故障模式，即使不滿足t -可診斷性，大大減少了系統級故障診斷的復雜度，尤其是對強t -可診斷系統；首次分析探討了各類測試模型的方程解決，由此從另一角度能系統地、高效率地求出所有的相容故障模式（ cfp ） ：擴充了系統級故障診斷模擬系統的功能，快速、直觀和隨機地模擬實驗運行環境，進行清晰和正確的診斷，同時提供大量的實驗數據用於理論研究，優化演算法和設計。 -
Business logic in the form of chained message processor components can be easily configured at a fix session level
即插即用的業務邏輯可在fix對話層簡易配置連鎖式信息處理器組件的業務邏輯。 -
As a crucial embedded development tool, the embedded system debugger is usually used to debug and test embedded software 。 a embedded system debugger consists of a cross debugger and a debugger agent, which characteristic lies in the separation of running environments between the cross debugger and the debuggee and the dependence on the gdb agent in the debug session 。 with the development of embedded technique, various embedded debug techniques continuously advance and all kinds of embedded system debuggers are playing a more and more important role in the embedded software development 。 the gnu debugger, gdb as a tool in the gnu toolkits, is an extremely powerful source - level debugger 。 among gdb ’ s many noteworthy features, its ability to debug programs “ remote ” is fascinating 。 this capability is not only essential when porting gnu tools to a new operation system or microprocessor, but it ’ s also useful for developers who need to debug an embedded system based on a processor that gnu already supports 。 gdb is the preferred solution in embedded development because it provides portable, sophisticated debugging over a broad rang of embedded systems 。 this paper discusses the status quo of various embedded system debuggers ; deeply analyses the overall structure of gdb and the debugging mechanism of gdb based on its source codes ; introduces the gdb ’ s remote debug technique and gdb / mi, which are usually used to develop the gdb - based embedded system debugger 。 then dwells on how to use gdb / mi to develop a gui front and how to use rsp 、 stub and gdbserver to design a debug agent, in order to expatiate on the design method of the gdb - based embedded system debugger 。 in the end, provides a concrete implementation of the gdb - based embedded system debugger of “ embedded simulation development platform ”, the project of the innovation fund for technology based firms 。
這個特性不僅在將gnu工具移植到一個新的操作系統和微處理器的時候很有用，對于想調試一個基於gnu支持的晶元的嵌入式系統的開發人員來說，也是非常有用的。由於gdb提供了在大多數嵌入式系統上的可移植的、復雜的調試功能，它已成為嵌入式開發的首選解決方案。本文討論了當前的各種嵌入式調試器的現狀，結合源代碼詳細分析了gdb的結構和調試原理，介紹了開發基於gdb的嵌入式系統調試器常用的遠程調試技術和gdb / mi介面;然後詳細闡述了如何使用gdb / mi開發gdb的圖形前端和怎樣使用rsp協議、 stub和gdbserver設計一個調試代理，從而較深入地討論了基於gdb的嵌入式調試器的設計方法;最後，結合國家中小型企業創新基金項目「嵌入式模擬開發平臺」 ，給出了一個基於gdb的嵌入式系統調試器具體實現。 -
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
In this paper, an embedded 16 - bit processor core is designed, based on the characteristics of the wireless communication algorithm and instruction level acceleration technology
文章結合無線通信處理演算法的特點，利用指令級加速技術，設計了一種基於無線通信中復數運算的16位嵌入式處理器核。 -
What i am saying is that i ' m optimistic enough to believe that within the next decade, we will see progress to a level that for things like dealing with data in a spreadsheet or text in a word processor, or navigating the internet, you will find the speech interface has enough accuracy that it becomes a primary way of interacting with the machine
我正在說是我夠樂觀來在下十年內相信那，我們將會看見對一個水平的進步為事物像由於數據處理在一臺文件處理機中的試算表或本文中，或航行英特網，你將會找演講介面有它變成的充足準確性一個主要的方式用機器互相影響。 -
The verification process for a digital signal processor with very long instruction word ( vliw ) named thuasdsp2004, which is developed by tsinghua university microelectronic institute sponsored by national natural science foundation, is analyzed at the register - transfer level in this paper
本文介紹在國家自然科學基金的資助下，由清華大學微電子研究所設計的具有超長指令字（ verylonginstructionword ， vliw ）體系結構特點的數字信號處理器thuasdsp2004的rtl級功能驗證工作。 -
2. the design of low - level driver of powerpc 405. after thoroughly collecting and consulting the latest information in the field of sopc, in this thesis we choose fpga embedded powerpc405 processor hardcore to construct the demanded sopc system, which manages to meet the application demand between
論文課題在認真深入地調研了國內外sopc領域的最新資料后，選擇了嵌入powerpc405處理器硬核的fpga片上可編程系統，解決vxi介面與本地ram控制器的通訊和靜態存儲器存儲控制等方面的應用需求，通過powerpc硬體設計和底層驅動軟體編程，構建了滿足設計需求的高速數字測試系統。 -
This thesis mainly focuses on the multi - level parallelism development and performance optimization of scientific programs on this architecture, and our works are summarized as follows. ( 1 ) we put forward the multi - level parallel computing time model, which is suitable for smp cluster to analyze program performance from the micro - aspect. we also provide a multi - level parallel optimization speedup model based on the single - processor speedup factor, which can evaluate program performance from three parallel levels and guide us to improve the programs
本文圍繞這種多級并行體系結構中的超節點級、節點級和單機指令級三個層次的并行性開發與優化，在科學計算程序的綜合優化技術研究方面做了以下的工作與創新: （ 1 ）針對smp集群體系結構提出了多級并行計算時間模型，用於程序性能的微觀分析;將單機處理速度與加速比統一起來，提出了基於單機優化加速因子的多級并行優化加速比評價模型，該模型分別從三個并行層次的角度出發對程序性能進行評價，並指導對程序的改進與優化。 -
In word processing, an interface device which connects to a typewriter converting it into a low level word processor
字（詞）處理技術中採用的一種介面裝置，當把它接到一臺打字機上時，可以將它轉變成一臺低級文字處理器。 -
By combining the system developing levels with the application environment, the redundancy level was positioned in the model - level redundancy, a / d connected in series with the master as the redundant unit, the bi - processor models drive on outer model
結合系統開發層次與使用環境，將冗餘級別定位於模塊級冗餘，提出了以a d與主機串聯形成的處理器模塊為冗餘單位、雙處理器模塊共同驅動一套外設的模型。 -
The pvr is a 32 - bit read - only register that identifies the version and revision level of the processor
Pvr是一個32位只讀寄存器，標識處理器的版本和修訂級別。 -
It ’ s a 16 / 32bits risc cpu based on arm920t ip core, which is highly integrated and powerful. this cpu has a lot of peripheral interfaces and i / o ports, which will facilitate our system design. the asic ime6400 is a system level chip which supports the multi - channel mepg4 video / audio compression. in our design, it ’ s served as an video compression oriented co - processor working under the control of s3c2410x. s3c2410x will do the job of importing the other vehicle traveling data such as analog and switch signals
在筆者設計的系統中， ime6400作為專門進行數字視頻信號壓縮的協處理器，與s3c2410x協同工作，完成視頻信號的獲取，壓縮等工作;同時利用晶元的片內外設（如ad轉換器和i / o口） ，完成汽車行駛過程中開關量和模擬量的獲取和存儲，以滿足一個記錄儀的基本功能需求。 -
Consequently, an urgent problem is to ensure the tolerance of hardware error, to strengthen the tolerance of software error, to integrate hardware and software fault - tolerant technique in operating system level. based on the above analysis, this thesis researches the techniques of reliability and multi - processors system and proposes a fault - tolerance real - time embedded multi - processor system based upon the loosely coupled multiprocessor architecture
在此基礎上，本文對容錯關鍵技術和多處理器系統進行了深入地研究，結合多處理器結構和現代操作系統的分層結構思想，提出了一種基於松耦合多處理器體系結構的實時嵌入式容錯系統設計方案，以達到從整體上提高系統可靠性的目的。 -
3 ) the instruction - level parallel calculation of streamlines on 3d curvilinear grids has been implemented firstly by using the streaming simd extensions ( sse ), which are a set of extensions of the intel pentium hi / 4 processor. compared with the conventional algorithm, sse - based algorithm coded by vector class library enhances performance about 55 %, and coded by inlined - assembly is about 75 %
） pentium （ pentium4 ）處理器的流simd擴展（ sse ） ，首次實現了3d曲線網格流線計算的指令級并行，與傳統演算法相比，向量類庫編碼實現的sse演算法將性能提高了55左右，嵌入匯編實現提高了75左右。 -
In designing or selecting a topology for a parallel processing system, one fundamental consideration is system - level fault tolerance. in order to improve the fault tolerance, the paper analyses from the two following sides : one is by adding the less links related to the original networks, modifying the topology of the original one, we get higher fault tolerance of the new network ; the other is under the same topology network, ignoring the likelihood of one processor and ail its neighbors failing at the same time, or considering the distribution of the faulty nodes, that is studying the fault tolerance under the conditional connectivity or cluster - fault - lolerance
本文以提高網路的容錯度為目的，從兩個方面分析互連網路的容錯性質：一是在原網路基礎上增加少量連接，使新型網路具有更高的連通度（容錯度為連通度減1 ） ；二是在給定互連網路拓撲結構下，考慮故障處理器發生的概率和故障處理器的分佈狀況，在其中的某一具體條件下，即在條件連通度和簇容錯下分析互連網路的容錯性能，從而得到更高的網路容錯度。 -
Bbl back - side bus logic. logic for interface to the back - side bus for accesses to the internal unified level two processor cache
後端總線邏輯。訪問內部統一二級處理器緩存的後端總線介面邏輯。 -
A real - time data acquisition system with single - chip processor is introduced in this paper. it can monitor a lot of - ray charge level indicators simultaneously
摘要利用單片機組成實時採集系統，實現一臺儀器同時監控多個射線料位測量點。 -
Additionally, the continuous growing integration level allows the smaller processor size, which results in more complex internal architecture
越來越高的集成度使處理器體積變得更小內部結構更復雜。 -
A software development tool that translates high - level language programs into the machine - language instructions that a particular processor can understand and execute
把高級編程語言程序轉換到只有特定的處理器能了解和執行的機器指令的一種軟體開發包。
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