quiescent voltage 中文意思是什麼
quiescent voltage
解釋
靜態電壓-
The typical performance characteristics include : line and load transient response, efficiency, output voltage ripple, quiescent current, maximum load current, output voltage temperature characteristics and the short
其中，整體模擬指標包括:晶元線性調整率和負載調整率、轉換效率、輸出電壓紋波、晶元靜態電流、最大負載電流、輸出電壓溫度特性及短路負載電流。 -
The driver has the quiescent current under 1 a and also has soft - start circuitry to limit inrush current flow at power up. the chip can be operated normally in the temperature range of - 40 to 85 according to the simulation results. the brightness of the white leds can be controlled by using a dc voltage or a pwm signal applied to the pin with a few external components added
系統採用0 . 5 mcmos工藝;輸入電壓范圍為2 . 7v到5 . 5v ;在關閉狀態下消耗電流小於1 a ;具有軟啟動功能，可減小啟動過程中的浪涌電流;具有短路及過熱保護功能，工作溫度范圍為- 40至85 ; led亮度控制可以通過外加dc或pwm電壓信號和很少的外部元件實現。 -
( 5 ) designed the synthetic jet actuators and the testing system. experimented it in quiescent air, and analyzed the actuator ' s influence factors, such as voltage magnitude and frequency. the results agreed with the conclusions that made from theory analysis and numerical simulation
（ 5 ）基於設計的合成射流激勵器及測試系統，在靜止大氣環境進行了初步原理性實驗，並對激勵電源電壓幅值和頻率對合成射流的影響進行了分析，實驗結果與理論分析及數值模擬結果相吻合。 -
At quiescent conditions, the power supply voltage appears on the plate ( minus a little loss due to the ir loss in the transformer
在靜態條件下，高壓直接加載在屏級上（減去一點在變壓器初級的直流電阻上的損失） 。 -
For the convenience of test, varied circuit chip defects caused by the production process are abstracted as all kinds of models. at present the commonly used fault models mainly consist of stuck - at fault, stuck - open fault, bridge fault, store fault, delay fault, etc. testing methods based on voltage testing mainly aim at stuck - at fault model and have also obtained satisfactory result in research for many years. bridge fault is tested easily by quiescent power supply current ( iddq ) testing method. in regard to stuck - open fault that is difficult to testd by quiescent power supply current ( iddq ) and voltage testing, it can is tested by the dynamic current ( iddt ) testing
為了便於測試，我們將生產過程中集成電路出現的多種多樣的缺陷抽象為各種模型。目前常用的故障模型主要有:固定故障，開路故障，橋接故障，存儲故障，時滯故障等。電壓測試主要針對固定型故障模型，多年的研究也取得了令人滿意的結果; cmos電路中的橋接故障則宜用穩態電流測試方法（ iddq ）測試;對于電壓和穩態電流難以測試的開路故障，可以使用瞬態電流測試（ iddt ）的方法進行測試。 -
But often what is not obvious when reading a manufacturer ' s data sheet is how the initial accuracy of the device is affected by other key device parameters such as line regulation, load regulation, initial voltage error, output voltage temperature coefficient ( tc ), output voltage noise, turn - on settling time, thermal hyste - resis, quiescent supply current, and long - term stability
但，人們閱讀廠家的數據手冊時，因受諸如（電源電壓）線性調整率、負載調整率、初始電壓誤差、輸出電壓溫度系數tc 、熱遲滯（系數） 、靜態電流和長期穩定度等參數的影響而使初始精度往往不明顯。 -
In the fifth chapter, a new fully differential operational amplifier with voltage and current - mode negative feedback has been proposed, which can stabilize its quiescent operation point, using the characteristic of mos transistors which operate in the triode region acting as active variable resistor, a fully differential fourth - order chebyshev low - pass filter with tunable frequency and bessel low - pass filter with accurate group delay based on r - mosfet - c and operational amplifier has been designed
第五章：提出了一種新的既具有電壓共模負反饋又同時具有電流共模負反饋的全差分運算放大器電路，能較好地穩定電路的靜態工作點，並應用mos管工作在線性區可作有源可變電阻用的特性設計得到了截止頻率可連續調節的高性能r - mosfet - c 、運放結構切比雪夫（ chebyshev ）和精確群時延值貝塞爾（ bessel ）低通濾波器。 -
In the early 1980 ’ s, quiescent power supply current ( iddq ) testing method was proposed in cmos testing. testing method based on current testing have very good compatibility with cmos circuits, it can detect some faults and physical defects those cannot be detected by testing methods based on voltage testing
基於電流的iddq測試方法與cmos電路有很好的兼容性，它可檢測出電壓測試方法不能檢測的故障和物理缺陷，目前已成為一種廣為接受的重要的cmos數字集成電路的測試方法。
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