register memory 中文意思是什麼

register memory 解釋
寄存奇儲器
  • register : n 1 記錄，注冊，登記，掛號。2 （人口動態，戶籍等的）登記簿，注冊簿；【商業】船籍登記簿；海關證明...
  • memory : n. 1. 記憶；記憶力；【自動化】存儲器；信息存儲方式；存儲量。2. 回憶。3. 紀念。4. 死後的名聲，遺芳。5. 追想得起的年限[范圍]。
  1. Core memory register

    磁心存儲寄存器
  2. A pulse to gate the output of a core memory sense amplifier into a trigger in a register

    一種只讀存儲器，其中的內容可以擦除，使存儲器成為空白狀態。
  3. Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel

    這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。
  4. Risc processors generally feature fixed - length instructions, a load - store memory architecture, and a large number of general - purpose registers and / or register windows

    Risc處理器一般的特徵是固定長度的指令集，一個負載儲備存儲結構，和大量通用寄存器，及寄存器窗口。
  5. Memory management is simpler when all processes use the same segment register values when they share same set of linear addresses

    當所有的進程都使用相同的段寄存器值時（當它們共享相同的線性地址空間時） ，內存管理更為簡單。
  6. The information of running programs users can get is just the register, memory and symbol state

    所看到的程序執行現狀，也只是目標機方當前程序寄存器、內存、符號信息等基本信息。
  7. The most common analysis is data dependence analysis, which is to determine the i tructio that use the variable ( register or memory location ) modified by another i truction

    最通常的分析是數據依存性分析，它用來確定指令使用的變量（寄存器或內存位置）是否被另一條指令修改。
  8. The most common analysis is data dependence analysis, which is to determine the instructions that use the variable ( register or memory location ) modified by another instruction

    最通常的分析是數據依存性分析，它用來確定指令使用的變量（寄存器或內存位置）是否被另一條指令修改。
  9. These allow you to stop at procedure locations, inspect memory and register values, change variables, observe message traffic, and get a close look at what your code does

    這些功能使您可以在某些過程位置停止執行，檢查內存和寄存器值，更改變量，觀察消息通信量，以及仔細查看代碼的行為。
  10. For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively

    摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。
  11. For example, a compiler may choose to optimize a loop index variable by storing it in a register, or the cache may delay flushing a new value of a variable to main memory until a more opportune time

    例如，編譯器為了優化一個循環索引變量，可能會選擇把它存儲到一個寄存器中，或者緩存會延遲到一個更適合的時間，才把一個新的變量值存入主存。
  12. In both cases we can derive data dependences from reaching definitions and uses information obtained by data flow analysis. at schedule time true register dependencies are known, so register analysis does not involve any complication. but for memory dependencies we have to deal with the problem of aliasing ( addresses are computed during execution )

    而對于存儲器訪問指令而言，其相關性分析則相對復雜得多，關鍵問題是必須解決存儲器訪問地址的別名問題（ aliasingproblem ） ，即必須判斷出對存儲器的兩次訪問是否針對同一個地址單元，然後在此基礎上進行存儲器訪問的數據相關性分析。
  13. Controlling system is composed of drive circuit, locking memory, shift register. temperature compensating circuit and drive power circuit are also needed

    控制系統是由驅動電路、鎖存器、移位寄存器等組成，此外還需要溫度補償電路和驅動電源電路，本文對控制系統進行了詳細的論述。
  14. This program memory addressing logic is handled by a register referred to as a program counter.

    程序存儲器的導址邏輯是由寄存器來實現的，這個寄存器叫程序計數器。
  15. Each time a segment selector is loaded on to segment registers, the corresponding segment descriptor is loaded from memory into a matching non - programmable cpu register

    每次將段選擇器加載到段寄存器中時，對應的段描述符都會從內存加載到相匹配的不可編程cpu寄存器中。
  16. Memory buffer register

    記憶緩沖緩存器
  17. Rtos - 1750 make use of static memory management to implement memory protection provided by page register ' s memory mapping and bpu ( block protect unit ), with which system keep fast reference as well as relatively independence by the technology of strding - mapping. system manages inner interrupt and outer interrupt by priority classing strategy and provides four type timers, which are system timer, software timer, auxiliary timer and real - time timer

    系統充分利用1750a提供的頁面寄存器堆的內存映射功能和塊保護單元（ bpu ）提供的存儲器保護功能，採用靜態內存管理方式，既保證了任務之間的相對獨立，又通過跨段映射技術滿足了dcmpofp中的任務快速引用的要求。
  18. The filter in bpf was implemented by a pseudo machine, which consists of an accumulator, an index register, a scratch memory store, and an implicit program counter. bpf can be directly programmed via ioctl system call and the pseudo machine instruction set, it can also be programmed by using libpcap function library, which can access many kinds of packet capture facilities provided by oses ( bpf is the important one in them )

    Bpf的過濾器是由假想的過濾器虛擬機實現的，對bpf的編程，可以通過ioctl系統調用和過濾器虛擬機的指令集來直接編程，也可以通過libpcap提供的庫函數來編程，它能訪問許多種操作系統內核提供的包過濾設施（ bpf是其中重要的一種） 。
  19. Intel architectures use a segmented address space in which memory is broken up into 64kb segments, and a segment register always points to the base of the segment that is currently being addressed

    Intel架構使用了分段的地址空間，其中內存被劃分成64kb的段，有一個段寄存器總是指向當前正在尋址的段的基址。
  20. The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method

    這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。
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