sdram 中文意思是什麼

Double data rate - synchronous dram, ddr - sdram

雙倍數據傳輸率

Sdram synchronous dynamic random access memory

同步動態隨機存取存儲器同步內存

Sdr sdram single date rate

單數據率

Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。

In the third chapter, the hardware design of the radar echo simulator is introduced, including the unitary chart of hardware structure and design of each part in this system, which is composed of designs of computer interface, controlling sdram and controlling ide harddisks and some introduction about d / a and fpgas used in this system

再次，介紹了本雷達回波模擬器的硬體設計，包括總體硬體結構框圖、系統各部分的硬體設計。系統各部分的硬體設計包括計算機介面設計、大容量高速緩存sdram的控制設計、 ide介面硬盤的控制設計、關于d / a的介紹和本系統使用的fpga的介紹。

The image compress flatform using dsp chip, image processing chip and sdram is designed and implemented. the jpeg arithmetic based on general image compress flatform is realized

採用dsp晶元、視頻處理晶元和sdram等器件，設計實現了圖像壓縮平臺； （ 4 ）基於通用圖像壓縮平臺，編寫了靜態圖像壓縮jpeg演算法。

Followed above, this dissertation has much content about the hardware design which include dsp, fpga, ddr sdram memory bank interface circuit, pci, power circuit, board - level interconnection design. this part puts much emphasis on key circuits many of which require us to have deeply known the components adopted and involved specifications

這部分主要是對電原理圖的重要地方和需要注意的地方進行重點闡述，包括dsp 、 fpga 、 ddrsdram內存條介面電路、 pci介面電路、電源、板級互連等部分。

Through the interface between the card and pc, the control infomation and dsp compression stage etc. can be conveniently notified. the simulation statistics indicates that the design mentioned in the paper can be conveniently and effectively appllied to the image processing card to accomplish the functions of the dataflow controls such as i2c operation 、 image transform parameter data transmission 、 sdr - sdram controller 、 pc - fpga communication, dsp video codec etc

驗證結果表明，本文所述的系統方案設計可以方便的應用在基於pc104總線的高解析度圖像處理系統中，並能有效完成i2c配置、 pc - fpga交互通信， fpga對sdr - sdram高速讀寫控制， dsp對圖像進行壓縮等系統功能。

The core of auto palm hardware is s3c2410a, one external 32m 8bits nadn flash is used to start and guide system, two external 4m 16 4banks sdram is used to execute main program code

掌上設備硬體是以三星公司的s3c2410a為核心，外擴兩片4m 16 4bankssdram用來執行主程序代碼，外擴一片32m 16bit的nandflash ，用來啟動和引導系統。

4. complete the design of system ’ s logic function with fpga. the sdram ’ s controller and ping - pong operation is studied, and the data ’ s continuous storage is also realized. 5

4 .設計實現系統的fpga邏輯部分，並研究了高速大容量sdram控制器和進行乒乓存儲操作邏輯時序，實現了數據流的連續傳輸。

The whole part of the data acquisition is build in a computer as two data acquisition cards. they are front card and rear card. the front card composed of four modules. they are : coin circuit module, data flow controller module, sdram array module and system bus interface module. the rear card composed of four odules. they are : asynchronous serial port interface module, adc control odule, ecg signal process module and gate control data produce module

數據採集模式實現部分的大部分工作是在前面板上完成的，後面板主要是一些外圍電路。前面板採集卡上從物理上來說主要有四塊電路:符合電路，數據流控制器電路， sdram陣列和系統總線介面電路組成。後面板採集卡從總體物理上主要有四塊電路組成: 485串列通信電路， adc控制電路，心電數據處理電路和門控信號產生電路。

The broadband signal is generated by high speed d / a, and the logical control of the system such as the interface timing control of ide or sdram is implemented by fpgas

採用高速d / a實現輸出信號的高寬帶，採用多片fpga完成整個系統的時序邏輯控制，比如ide介面時序的實現， sdram的操作等。

By the subtitle decoder, the subtitles will be held in sdram in the receiver

經由字幕解碼器，字幕可以被存入片外sdram 。

My task is to write the code of hdlc / laps, vc - 12 virtual concatenation and sdram interface. the design has been verified on hardware

本論文完成了上述的hdlc / laps協議處理、虛級聯處理、 sdram存取的設計及硬體驗證並通過了fpga實驗驗證。

With vc - 12 virtual concatenation, we can make efficient and flexible use of the bandwidth. sdram, as a mass storage medium, is applied also. in this design, i use hy57v643220ct - 6, with 32bit data width, up to 166m system clock, as the buffer of vc - 12 virtual concatenation alignment and ethernet data transmission

本論文設計系統中採用了現代的hy57v643220ct - 6作為外部存儲器，它的數據線是32位寬，保證了吞吐量，時鐘可高達166m ，保證了速度，用它實現了多個以太網發送端緩存和多路vc - 12虛級聯的對齊。

Sdram double date rate

雙倍資料傳輸率

North bridge is the center of communication with many high - speed buses and connects cpu, sdram, apg equipment and pci equipment. south bridge is connected to north bridge with pci bus, it has many low speed buses, such as isa, ide, usb, floppy disk, p / s2, serial port, parallel port. with its characteristic, this system has two million ethernet interfaces and one watch - control module

其中，北橋是整個系統的核心通信部分，含有豐富的高速總線介面，連接了cpu 、 sdram 、 agp設備和pci設備；南橋和北橋通過pci總線互聯，它引出的總線一般速率比較慢，如isa 、 ide 、 usb 、 floppydisk 、 p s2 、串口、並口等。

Embedded system is a computer system, which is focus on application, based on computer technology, and its software and hardware could be pruned, besides embedded system has particular requirement for its reliability, cost, volume and power consume. embedded system is relative to computer system structure, encode theory and work theory, and come down to all kinds of computer interface and memory technology, such as serial and network interface, flash and sdram memory technology. the processor and interface and memory device will be difference when referring to different applications, but, as far as the researching and developing method of embedded system, they are generally same

嵌入式系統是以應用為中心、以計算機技術為基礎、軟硬體可剪裁併對功能、可靠性、成本、體積和功耗都有嚴格要求的專用計算機系統，涉及計算機系統的體系結構、編譯原理和工作原理，涉及到計算機的各種介面和存儲應用，如常用的串口、網路控制等介面和flash 、 sdram等存儲技術，此外，因嵌入式系統的應用不同，處理器和介面及存儲設備都會有所不同，但就嵌入式系統的研究與開發方法來說有許多相同之處，因而深入研究和設計某種嵌入式系統具有深遠的意義。

This system is developed based on high performance, low cost and many controllers inside of the embedded processor, and enlarged gpio for the plat of the hardware and software. this system is applied to the high - speed numerical control carving machine. show the operate interface by lcd, input the control code from the keyboard, the data is readed from the usb interface and store that in sdram

本系統應用於高速數控雕刻機，以lcd為人機可視化操作界面，以編碼鍵盤為操作控制部分，以嵌入式處理器s3c44b0x晶元為核心，文件數據經usb口讀取u盤中的雕刻數據文件暫存於sdram中，經嵌入式處理器進行相關演算法處理，得出相應參數傳送到fpga ，由fpga控制輸出脈沖和脈沖間延時，通過高速光耦隔離（ 2mbit / s ）后輸出，控制步進電機的運轉。

High - effective and low - cost memory system the demand for bandwidth and response time of video decoder is analyzed, a high - effective and low - cost multi - entity interlaced ddr sdram controller design and relevant address mapping scheme is proposed

高效低成本的存儲系統設計本文分析了avs和h . 264解碼器對存儲系統帶寬和響應速度的要求，針對ddrsdram延遲長、多bank的特點，設計了一套高效的多體交錯式ddrsdram控制方案和相應的地址映射方式。