set processor 中文意思是什麼

set processor 解釋
組處理機
  • set : SET ＝safe electronic transaction 安全電子交易〈指用信用卡通過因特網支付款項的商業交易〉。n 【埃...
  • processor : n. 1. 〈美國〉農產品加工者；進行初步分類的人。2. （數據等的）分理者；【自動化】信息處理機。
  1. Through researching the present mainstream ip set - top box hardware system, designed an ip set - top box system which based on the adi blackfin series dsp, and chose the bf561 processor as the system core processor

    本文通過對目前主流ip機頂盒硬體系統的研究，設計了一種基於adiblackfin系列dsp的ip機頂盒方案，並選擇了blackfin系列中的雙核處理器bf561為本系統的核心處理器。
  2. In practical studies, finally, a hybrid active power filter based on the digital signal processor ( dsp ) and intelligent power module ( ipm ) was set up, including a cycloconverter acem. based on the experimental set - up, plenty of experimental studies were conducted. the experimental results demonstrate that the self - adaptive technique, the topology of series connected hybrid power filter and the corresponding significant technologies described above are feasible and practical

    最後，實際研製了一套以dsp （高速數字信號處理器）和ipm （智能功率模塊）為核心的小功率混合型有源濾波裝置，在交交變頻acem實驗平臺上進行了全面的實驗研究，充分驗證了本文所提出的自適應同步相關濾波技術、優化混合型濾波器拓撲結構和有關的關鍵性技術的正確性和實用性，從而從理論到實踐全方位、成功地實現了對交流勵磁發電機輸出電力諧波抑制的研究。
  3. A processor is composed of two functional units ? a control unit and an arithmetic / logic unit ? and a set of special workspaces called registers

    處理器由兩個功能部件（控制部件和算術邏輯部件）與一組稱為寄存器的特殊工作空間組成。
  4. This paper introduces a ip phone system based on dsp and arm reduced instruction set computer ( risc ) double core processor

    本文介紹的是一種基於dsp和arm精簡指令集處理器（ risc ）雙cpu處理器方案研發的ip電話系統。
  5. Firstly, the thesis summarizes and dissertates the theory and key technologies of miniature intelligent reading system, analyzes the characteristics, application prospects and the working proposal, and further more, brings forward a complete set of schemes, on this foundation, fulfills the hardware construction with the dsp serving as core processor

    本文正是針對這種現象，結合新興技術，對基於dsp的微型智能閱讀系統進行研究並提出了一種解決方案。本文首先對微型智能閱讀系統理論及其關鍵技術進行了概括和論述，分析論證了系統特點、應用前景以及工作原理，提出了一種系統整體解決方案，在此基礎上完成了以dsp為核心處理器的硬體架構。
  6. Computer control is easy through the ieee - 488 interface, or via the second rs - 232 port. since all channels perform their own processing and the i o is handled by the main processor, the power analyzers offer unparalleled interface speed. twelve analog and 16 digital outputs can be set to track and alarm on specific parameter ranges

    經由ieee - 488或rs - 232埠可提供簡易的電腦控制，由於所有通道均進行固有的處理及由主處理器管理i 0 ，功率分析儀遂能提供非平行式的介面速度， 12個模擬和16個數字輸出可被設作追蹤與警報特殊參數范圍
  7. Hardware design uses high - speed digital signal processor tms320lf2407a as the key control part. software design adopts hexagon stator flux scheme and round stator flux scheme respectively. after the system is set up, the direct torque control method is realized for a 0. 12kw winding asynchronous motor

    最後根據以上的討論和實際應用中的情況，分別採用六邊形磁鏈方案和圓形磁鏈方案，以高速數字信號處理器ths320lf2407a作為核心控制部件，在一臺0 . 12kw的繞線式異步電機上實現了異步電機直接轉矩控制。
  8. The pre - processor works with a set of regexes called a

    預處理程序是用一組正則表達式（稱為
  9. The author designed and developed a single phase mid - frequency inverter control unit, which is based on dual micro - processor system. the inverter is modulated by pre - set spwm pulse width wave

    本文研製出一種基於雙微處理器（ mpu ）控制的單相中頻逆變電源控制裝置，逆變電路基於開關預置spwm波脈寬調制。
  10. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution

    基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。
  11. Harmonic analysis can be produced in as little as 10 milliseconds, or measurements may be integrated over more than a day. the user may set any measurement interval, perform synchronous averaging on harmonics, and even perform full spectrum analysis to detect non - harmonic signal content. the system s main processor controls all display, data storage and i o functions, thus allowing each channel to perform its analysis at maximum speed

    在每通道雙數字信號處理器結構中，結果形成超快速諧波分析，諧波分析可於至10毫秒產生，或可綜合測量超過一天，用戶可設定任何測量區間，執行諧波同步平均，及進行全頻譜分析從而探測非諧波信號內容，系統的主微處理器控制全部顯示數據儲存與i 0功能，故使各通道可於最高的速度下進行分析
  12. The processor affinity could not be set

    未能設置處理器關聯。
  13. The processor affinity of a thread is the set of processors it has a relationship to

    線程的處理器關聯是線程與其有關系的一組處理器。
  14. The asp. net process model helps enable scalability on multiprocessor computers by distributing work to several processes, one per cpu, each with processor affinity set to a cpu

    Asp . net進程模型幫助啟用多處理器計算機上的可伸縮性，方法是將工作分發給多個進程（每個cpu一個） ，並且每個進程都將處理器關聯設置為一個cpu 。
  15. There are technologies that allow you to allocate software execution to a set number of processors sometimes called processor pinning

    有些技術允許將軟體執行分配到一組處理器上（有時候也叫做processor pinning ） 。
  16. Instructions produced for the default processor may be outside the set of instructions understood by the host processor

    為默認處理器生成的指令可能超出主機處理器所能理解的指令集的范圍。
  17. In order to generate the exact set of the host processor s instructions, the jit compiler needs to precisely determine the architecture type of the underlying processor

    為了生成主機處理器的正確的指令集， jit編譯器需要明確地確定底層的處理器的體系結構類型。
  18. And asip ( application - specific instruction set processor ) based on risc core is the key to integrate other system

    而基於risc核的專用指令處理器（ application - specificinstructionsetprocessor ）是構成其它更大系統的關鍵。
  19. To solve the problem of exponential space in the instruction - set automated design for the application specific instruction set processor ( asip ), a formular clustering integer linear programming model ( cim ) is proposed, which can decrease the exploration space effectively utilizing function dependencies between instructions

    摘要提出集束式整數線性規劃形式化模型，利用指令間的功能依賴性解決專用指令集處理器中指令集自動定製的指數性空間問題。
  20. Technique of attribute weights extraction in application specific instruction set processor design

    評估指標權重抽取技術
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