signal gate 中文意思是什麼

signal gate 解釋
信號門
  • signal : n 1 信號，暗號；信號器。2 動機，導火線 （for）。3 預兆，徵象。adj 1 暗號的，作信號用的。2 顯著的...
  • gate : n 1 大門，扉，籬笆門，門扇。2 閘門；城門；洞門；隘口，峽道。3 【冶金】澆注道，澆口，切口；【無線...
  1. The method can be used in the measurement of periodic and nonperiodic signal. according to the high accuracy and fixed gate - time measurement method, based on the multiple period synchronization method, the high speed, high accuracy and continuous frequency measurement is accomplished

    將其再與一種從多周期同步法發展而來的高精度、定閘門法相結合，從而實現了高速、高精度、連續頻率測量，這非常適合非頻率量的頻率傳感信號的測量。
  2. This thesis primarily discussed the baseband processing of ss communication signal based field programmable gate array ( fpga ) asic chip

    本論文主要討論和實現了基於fpga的擴頻通信信號的基帶處理。
  3. The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5

    電平調節電路100將送往第一個時鐘終端ck1的時鐘信號從h電平降低一個預定值，並將此信號送往晶體管q5的輸入端。
  4. In gan hemt drain pulse current collapse experiments, drain current under pulse condition collapsed about 50 % than direct current condition and the pulse signal frequency affected little on current collapse. when gate voltage is small, the relationship between pulse width and drain current is i0 ( + t / 16 )

    在ganhemt漏極脈沖電流崩塌測試中，發現脈沖條件下漏極電流比直流時減小大約50 % ;脈沖信號頻率對電流崩塌效應影響較小;當柵壓較小時，隨著脈沖寬度的改變漏極電流按i0 （ + t / 16 ）的規律變化。
  5. The trigger electronic module consists of 3 discriminators and a coincidence unit which performs a 2 - out - of - 3 logic gate. hence either 2 detectors or 3 detectors receiving cosmic ray signal will trigger daq

    觸發電路模組由三個鑒別器和一個與門電路組成。當有兩塊或以上的探測器同時產生訊號，該電路便會觸發數據收集。
  6. In the synchronous " model, based on the idea of polygonal flux linkage locus, by means of constructing the switch state period table of three phrase voltage inverter is required. in the brushless model, the igbt ( isolated gate bipolar transistor ) switch state period table is gained by gal ( generic array logic ) which analyzes the signal of position feed - back

    在同步方式下，基於多邊形磁鏈軌跡法的思想，用作圖法求得三相電壓型逆變器的pwm波形序列；在無刷直流方式下，用gal對位置反饋信號進行邏輯綜合，得到開關管的導通規律。
  7. The whole part of the data acquisition is build in a computer as two data acquisition cards. they are front card and rear card. the front card composed of four modules. they are : coin circuit module, data flow controller module, sdram array module and system bus interface module. the rear card composed of four odules. they are : asynchronous serial port interface module, adc control odule, ecg signal process module and gate control data produce module

    數據採集模式實現部分的大部分工作是在前面板上完成的，後面板主要是一些外圍電路。前面板採集卡上從物理上來說主要有四塊電路:符合電路，數據流控制器電路， sdram陣列和系統總線介面電路組成。後面板採集卡從總體物理上主要有四塊電路組成: 485串列通信電路， adc控制電路，心電數據處理電路和門控信號產生電路。
  8. The digitizer based on pxi bus uses fpga ( field programmable gate array ) to implement 256 points, radix - 2 dit fft ( fast fourier transform algorithm ). the design uses pipelining for fft processing and can accomplish sampling and processing signals of two channels at the same time. in the signal acquisition circuit, - a / d convector is used to enhance the precision of the signal sampling

    在本設計中，採用fpga （ fieldprogrammablegatearray ）實現了256點基2dit演算法復數fft （ fastfouriertransformalgorithm快速傅氏變換演算法）處理器，具有較高的速度和運算精度fft ，設計採用流水線處理方式大大的提高了處理速度，可實現對兩個通道輸入信號的并行採集與處理。
  9. The problem in high speed signal process, such as parasitic parameter and gate delay is also the difficulty hi the research

    生成高速，穩定的時鐘信號是本課題的目標。高速信號處理所遇到的常見問題，如寄生參數，門電路延遲是設計難點。
  10. The output signal can then be amplified ( possibly with a logic gate at this point ) to drive the converters

    電路輸出的信號需要放大后再使用（例如用邏輯門） 。
  11. The system will display the gate status, the thunder status and fire signal status. it allows the management clearly receiving running status of all facilities and subsystems in the central control room. the system graphically displays the alarm position, informs management by phonetic alarm and provides relevant disposal method for the management, which reduce cost of undesired contingency

    虹口稅務局基於節能和高效管理的考慮，在夜間，如果雙鑒探頭檢測到有人活動，則自動控制燈光開啟與關閉，同時聯動視頻進行錄像，並在界面上實時反映門的開關狀態防雷的狀態消防信號的狀態等，讓機房管理人員通過機房監控系統統能夠全面地了解機房內所有設備和子系統的運行狀態，並形象地顯示報警發生的位置，進行語音提示，同時提示相應報警的處理方法，將損失減少到最小。
  12. A high - speed sampling system for echo signal of impulse gpr based on equivalent time sampling method is presented, and significant circuits including step sampling pulse generator and sampling gate circuit are designed

    摘要提出了一種基於等效時間采樣方法的沖擊型探地雷達回波信號高速采樣系統，設計實現了等效時間采樣的關鍵電路，包括步進采樣脈沖發生器、采樣門電路。
  13. This paper demonstrates how to generate variable pwm waveform based on standard cpld device, the proposed circuit is incorporated with mcu to provide simple and effective solution for high - performance pwm converters. in the brushless model, the igbt ( isolated gate bipolar transistor ) switch state period table is gained by mc33035 which analyzes the signal of position feed - back

    這部分功能在cpld器件中用vhdl語言開發實現，其isp （在系統編程）方式使得設計與維護都比傳統方法方便靈活，由於逆變器開關元件的觸發信號是由硬體來產生的，因此更容易實現準確的高速實時控制。
  14. And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time

    其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。
  15. An electrical gate or mechanical device which implements the logical or operator. an output signal occurs whenever there are one or more inputs on a multichannel input. an or gate performs the function of the logical " inclusive or operation "

    一種實現邏輯「或」演算法的門電路或機械器件。當在其多通道輸入端有一個或多個輸入時就產生一個輸出信號。 「或」門實現邏輯「或操作」的功能。同orelement 。
  16. For the high - speed digital signal processing, the structure of fpga and dsp is widespreadly adopted. dsp is more featured in the implementation of complicated algorithm, while field programming gate array ( fpga ) shows more advantage in its flexibility of design, simplicity of system configuration, modification and maintenance. in the paper, the hardware system of the spaceborne radar is based on the structure of fpga and dsp, of which the signal processing part is accomplished with one fpga chip and multi dsps

    Dsp適合完成結構復雜的演算法;現場可編程邏輯陣列（ fpga ）適合完成高效、演算法固定的任務;與專用集成電路（ asic ）相比， fpga優點主要在於其很強的靈活性、可在線配置、修改和維護方便等優點。本文工程中的星載雷達信號處理和控制系統就是採用dsp + fpga的方式。其中信號處理採用的是xilinx公司的virtex -和virtex系列fpga和多片analogdevices公司的tigersharcts101的硬體電路結構。
  17. The main contents of the paper are : i the relationship of the accurateness of calculation, complexity of calculation and hardware resources of the 5 - 3 dwt ; ii the basic theory of pci data transmission the controlling of the host to client and the data exchanging ; iii configuration of the video decoder saa7114h to implement the transformation of the analog to the digital image ; iv image acquisition, compression and transmission from the host to the acquisition board by the component of field programmable gate array ( fpga ), digital signal processor ( dsp ) with the controller of pci and video decoder saa7114h

    Pci的數據傳輸原理，外部主機如何控制從屬設備以及如何進行數據交換。配置視頻解碼器saa7114h ，實現模擬ccd攝像頭模擬數據到數字數據的轉換，實現採集的功能。用fpga 、 saa7114h和集成pci介面的dsp實現圖像的採集、壓縮以及從採集板到主機的傳輸。
  18. The phase detecting error caused by local oscillator frequency drift and non - synchronization of measurement signal and gate signal is eliminated and the measurement speed is improved at the same time

    該方法可以有效的消除因本振信號頻率漂移及閘門信號與被測信號的非同步引起的測相誤差，同時提高了測量速度。
  19. Because of the asymmetry between sip protocol and h. 323 protocol, there are some difficulties in the course of realizing sgw ( signal gate way ) in softswitch

    摘要由於sip協議與h . 323協議之間的非對稱性，使軟交換信令網關在實現時將不可避免地遇到一些困難。
  20. 2. by analyzing the partial discharge signals and the interferences and using high - speed filed programmable gate array ( fpga ) and digital signal processor ( dsp ), a hardware and print circuit board have been designed 3

    2 ）通過對局部放電和干擾的分析，針對局部放電信號實時處理的要求，利用高速的現場可編程邏輯器件和數字信號處理器完成了信號處理的硬體電路板的設計與製作。
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