signal timing design 中文意思是什麼
signal timing design
解釋
信號時序設計；號志時制設計；號志時段設計-
This paper introduces common background knowledge of intersection, mainly describes traffic control design principle, such as signal timing and lane channelization. it also summarizes the same point between signal timing and lane channelization in nature and illustrates that it is optimal cycle length and signal phase that is the critical part of signal timing
=本文介紹了交叉口的一般背景知識，重點闡述了平面信號交叉口的交通控制的設置原理，包括信號配時原理和路口渠化原理，概括了信號配時和路口渠化原理的本質相同點。 -
The definition of high - speed circuit design as well as the signal integrity and timing problems in this design was introduced
摘要介紹了高速電路的定義以及在高速電路設計中存在的信號完整性、時序問題，詳細分析了產生這些問題的原因。 -
To develop a new approach so as to realize music fountain control with high quality, this paper describes the control design for music fountain system based on the industry personal computer. pwm frequency conversion timing, preprocessing, predicting and compensating algorithm, and software signal control in advance are adopted, which realize color music spring control with high quality, provide a new advanced method for the control design of music spring
本文採用pwm變頻調速、預處理、預測補償控制和基於數據庫的軟體信號提前控制方法，提出了一種新的先進的音樂噴泉設計方案和控制途徑，並與傳統設計方案進行了分析比較，用面向對象的編程方法完成了對當今較為流行的mp3音頻格式的解碼，同時實時提取了音頻信號。 -
Design a kind of sub - optimum digital prefilter. through the simulation of timing recovery loop which is n ' t added prefilter and which is added prefilter, discuss the convergence characteristic and compare the relation between timing jitter and signal to noise ratio, the relation between timing jitter and noise bandwidth of loop, the relation between symbol error ratio and signal to noise ratio
通過對加預濾波器后的定時恢復環的模擬，討論了環路的收斂情況，比較了所設計的數字預濾波器和無預濾波器時環路定時抖動與信噪比、定時抖動與環路噪聲帶寬、誤碼率與信噪比的數量關系，證實所設計的數字預濾波器對減少定時抖動非常有效。 -
It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface
本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。 -
Aiming at realizing an all - digital programmable qpsk modulator with data rates covering 2k ~ 2. 048mbps, this thesis puts research on modulator architecture, base - band signal shaping, programmable interpolation algorithm, and digital signal processing algorithms with fpga. we have completed the program design and the timing simulation, the pcb board has been fabricated. the similation result is given to verify the design
本文以實現2k ~ 2 . 048mbps傳輸速率的變碼速率全數字qpsk調制器為目標，對全數字調制器結構、基帶成形濾波、高倍可變內插以及基於fpga的信號處理演算法等問題進行了研究，編寫了調制模塊的vhdl程序，完成了軟體環境下的驗證調試，並設計實現了板級調試系統。 -
Simsio can provide a flexible and efficient experiment analysis tool that can be used to evaluate signal timing, geometry design and traffic management of signalized intersections, as well to test as new techniques and concepts. finally, application of simsiq in intelligent transportation system is viewed as a prospective trend. it is pointed out that the future development of expert system and simulation system are intelligent and integrated
在以上模擬模型的基礎上，提出simsio模擬系統面向對象的軟體設計方法、系統設計、系統實現、數據輸入以及模擬結果的輸出等內容，利用實測數據與simsio的模擬結果進行對比發現， simsio的模擬交通流與實際交通流在交叉口的交通運行描述上基本一致。 -
It includes geometric design, traffic organization design and signal timing of signalized intersection. the techniques of expert system and computer - based simulation are employed. several schemes that are generated from expert system of signalized intersection design are inputted into microscopic simulation system, and then optimal scheme is put forth
本文研究了城市道路信號交叉口的優化設計方法，具體的研究過程是：利用專家系統技術，從幾何設計、交通組織設計以及信號配時等三方面對信號交叉口進行優化設計，然後利用微觀計算機模擬技術對優化方案進行評價。 -
The thesis expounds the cell design and timing design of the fpga circuit in main controlling and baseband signal processing module, and develops the hardware of it, and programs part of the software
文中詳細闡述了主控與基帶處理單元中fpga模塊設計與時序設計，研製了主控與基帶信息處理單元硬體，編寫了部分調試軟體。 -
The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation
在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。 -
While designing the system, we spent a lot of time on considering how to divide and define each module and how to coordinate and interconnect these modules. we followed the top - down method to design. as for the interconnection of each module, we defined the interface signal to communicate between them, and the internal timing of the module was control1ed by states machine
在系統方案設計過程中，對模塊如何合理劃分及各個模塊之間如何協同工作做了仔細的推敲，按照自上而下的設計方法將各個模塊逐一細化，各模塊之間通過埠信號進行連接，模塊內部則由狀態機控制時序。 -
The thesis then introduces top - to - bottom schemes, which discuss the functional design of hdtv test pattern signal generator according to the tasks and platform of the system, and develops the function of subsystems. the thesis analyses the theory and mathematic model of hdtv test signal, and studies the signal generating scheme called single - fpga and multi - prom, and describes in detail its key modules such as configuration connecting, prom routing, control and switch timing design and so on. the single - fpga and multi - prom scheme increases the number of prom to reduce the degree of fpga demanded, thus
論文分析了hdtv測試信號的原理及數理模型，提出了一種以單晶元多配置為特色的信號生成方案，並對該方案的配置連接、晶元選路、控制切換時序設計等關鍵模塊進行了詳細敘述，該方案以增加配置晶元數量來降低對主晶元要求，不但降低了產品成本，還使各測試信號的代碼編寫和產生相對獨立，有利於合理使用晶元資源，實現多種復雜的hdtv測試信號，縮短開發周期。 -
This paper introduces some practicable ways to realize the design of background signal simulator console software, database exploitation and the data processing for the gps receiver ( gn - 79 ). to meet the needs of these superiorities such as simple maneuverability, modularization and high secrete security, we considerably think of those requirements in the aspects of the signal - producing, hardware - setting, timing and orientation, user setting and so on, during the period when we design the software, make the database accessing down to the bottom layer, and obligate full space for its improvements of software modification and function expansion
由於工程的操控部分即軟體實現部分需要體現簡便、易控、模塊化以及保密性好等優勢，因此，在設計實現操控界面的同時，充分考慮了信號產生、硬體設置、定時定位以及用戶設置等各方面的要求，實現了數據庫訪問技術到底層的管理，為將來的軟體修改、功能擴容留下了充分的空間。 -
Because the qam signal which is small roll - up factor has big timing - error jitter in steady state that result in big timing jitter, an expression of impulse response for digital prefilter is deduced and a kind of sub - optimum design method for digital prefilter is proposed in this paper
針對匹配濾波器滾降因子較小的qam信號的穩態定時誤差信號抖動較大，而造成較大定時抖動的情況。推導了一種用於減少定時抖動數字預濾波器的沖激響應表達式，並且提出一種數字預濾波器的設計方法，設計了一種優化數字預濾波器。 -
There is a strong relationship between the phase design and signal timing. the paper pays much attention to the expert system of multiphase design
然後利用以關鍵相位為基礎的配時模型進行研究，最終保證多相位信號方案的科學性和準確性。 -
Signal timing design
信號時序設計 -
To solve the problem associated with signal integrity, people more and more depend on use methodology based on circuit simulation, the basic principle is use simulation technology to solve the problem of signal integrity as more as possible in the early design, put forward the requirement to signal integrity, timing and emc / emi, satisfied manufacture and testing scheme and design principle, minimize product cost, reduce the project period
要解決信號完整性問題，人們越來越依賴于採用基於信號模擬的一體化設計，其基本思想為利用模擬技術，在產品設計早期盡可能的解決信號完整性問題，提出滿足信號完整性要求、時序要求、 emc emi要求，並滿足加工製造與測試的總體方案和設計準則，最大限度地降低產品成本，縮短研發周期。
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