stage chip 中文意思是什麼
stage chip
解釋
鏡夾-
After chip n dale, goofy and donald duck have warmed up the guests, the star of the show makes her appearance with mickey mouse then joining her on stage
首先上臺暖場的是奇奇帝帝高飛以及唐老鴨。接著可愛的女主角美妮將為您帶來色彩鮮明的拉丁舞。 -
It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。 -
The key stage of fabricating gene chip is pretreatment of glass surface including the processes of nh3h2o treatment, aminosilane treatment and aldehyde treatment. the pretreatment can grow active group that can bind probe effectively on the surface of glass slide. as a result, the actively treated glass slide can suit for fabricating in - situ synthesis high density gene chips
基因晶元制備技術的關鍵步驟是玻片表面預處理，即對玻片表面進行羥基化、氨基化和醛基化處理，使表面生長的活性基團能有效固定寡核苷酸探針，以滿足原位合成高密度基因晶元對玻片的要求。 -
Further, the characteristics such as the response speed, the efficiency and the relationship between load and the modulation factor are counted and analyzed. during the stage of circuit design, the whole chip and the sub - block circuits are well - designed, respectively
基於此模型，計算並分析了離散脈沖頻率調制下升壓型dc / dc變換器的響應速度、效率和負載與調制度的關系等特性。 -
At light loads, the architecture allows the chip to “ skip ” cycles to reduce power dissipation. in the circuit design, the basic principle and small signal model of the boost power stage are given at first, and then the stability and small signal model of the control loop are also analyzed, finally, the whole chip architecture and sub - block parameters are presented according to the application requirements
在電路設計中，首先闡述了升壓型直流轉換器的功率輸出級的拓撲結構、基本原理、小信號模型，然後分析了電流模式控制迴路的穩定性及小信號模型，最後根據應用要求進行了電路的總體架構設計，完成了每個子電路的各種參數的分析、計算。 -
At the logic synthesis stage, we make some research on the principles of logic synthesis at first, then by utilizing tsmc0. 25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2. 25v, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15. 3ns and the chip area is 0. 395mm2
在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然後利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，採用與模擬時相同的時鐘，關鍵路徑為15 . 3ns ，晶元面積為0 . 395mm ~ 2 。 -
The amplifier adopted the three - stage structure, and the first stage used one chip, the second stage used two chip in parallel, the third stage used four chip in parallel
該功放模塊採用三級放大結構，第一級採用一個管芯，第二級並聯兩個管芯，第三級並聯四個管芯。 -
The issue of itu g. 984 protocols has brought the recent research of gpon to the stage of chip designing
Itug . 984系列協議的發布標志著gpon協議體系的成熟，進入晶元設計階段。 -
Using pipeline technique to accomplish the most important operation in more than one stage, such as sad, which could not be finish in one pipeline stage at any cost. the on - chip memories and data path usually consume most percentage of power in media processor chip
數據通路的功耗也是dsp處理器功耗的重要部分，考慮採用門控時鐘技術防止mac模塊和alu模塊同時工作造成的功耗浪費，最後分析了md32晶元的功耗特徵。 -
As a result, there are some disadvantages for its large size, heavy weight and lower efficiency. in this paper, phase - shifted zero - voltage - switching pwm converter is presented, which is help to ruduce the size and improve the efficiency of inverter. in the later stage, we adopted a pic microcomputer as the control chip, whose low price decreases the price of the inverter
在逆變環節中，本文採用體積小、功能全、價格便宜而且簡單易學的單片機pic16c72作為控制晶元，對前級直流電壓進行spwm正弦脈寬調制，從而產生了高質量的正弦輸出電壓波形，減小了輸出電壓中的諧波含量。 -
In the stage of system debugging, the author used a microcomputer single chip to program an eeprom according to i " c bus criterion
在系統調試階段，還用單片機基於1 ~ 2c總線實現對eeprom編程。 -
Combining magnetic levitation technology and linear motor drive technology, applying cad / cae method, a new magnetic levitation precise stage is designed and researched, which is step and precise position mechanism in 1c chip manufacture equipment of micro - electronics trade such as laser photolithography equipment. it is an innovative research
將磁懸浮技術和直線驅動技術相結合，採用cad cae技術手段設計研究了一種新型磁懸浮精密定位工作臺，它是針對微電子行業ic晶元製造設備如光刻機而研製的快速步進、精密定位機構，是創新性研究。
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