stage routing 中文意思是什麼
stage routing
解釋
水位演算-
In the entitative routing stage, the macro - cell layout must be compressed for optimization area and time delay. it should be compared beauty with the routing result by manual. an algorithm, which is gridless, variable widths and minimizing layer permutation, is advanced for channel region
晶體管級實體布線階段，由於庫單元的復用性，要求庫單元版圖緊湊，即要求單元版圖在滿足各約束條件的前提下面積、性能優化程度較高，能與手工設計的版圖相媲美。 -
Finding a feasible and efficient load balanced strategy for the ultra - scalable multi - plane multi - stage switch architecture is a top of nowadays research. the dissertation proposes a two - stage load balanced scheme for the ultra - scalable multi - plane multi - stage switch architecture based self - routing and non - blocking permutation benes network. the approach uses reasonable and efficient logical queueing strategy and schedule scheme in ingress traffic managers and switch planes to realize the two - stage load balancing of ip traffic which for different destination addresses
本文提出一種適用於基於完全可重排無阻塞benes拓撲構建的多平面多路徑（多級）超大容量交換結構的兩級負載均衡策略，通過在輸入流量管理器和benes交換平面內部實施合理而高效的隊列組織調度方法，有效實現了基於不同目的地址的ip流量在兩個層次上的負載均衡，較好彌補了ciscocrs - 1系統在平面選擇和中間級選擇時所採用的簡單隨機或輪循方案的不足。 -
Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently
文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小 -
Describes the design and realization of partial run - time reconfigurable fpga in detail. in order to reduce the affect of the reconfiguration time on system execution time, mostly static circuit design method in logical design stage and incremental routing method in component implementation stage are proposed. the fft parallel processing algorithm is examined through vvp platform
本章詳細闡述了基於vvp平臺的多sharc功能插板的具體硬體實現，以動態重構fpga設計為核心，論述了局部動態重構fpga設計流程和方法，提出了極大靜態電路邏輯設計方法和遞增式布線方法，以達到減小動態重配置時間，提高系統運行效率的目的。 -
This paper deals with the problem of crosstalk mitigation at both methodological and algorithmic levels. noting that intermediate operations between global routing and detailed routing are very effective in crosstalk estimation and reduction, the authors propose to incorporate several intermediate steps that are separated in traditional design flow into an integrated routing resource assignment stage, so that the operations could easily cooperate to fully exert their power on crosstalk reduction. an efficient priority - based heuristic algorithm is developed, which works slice by slice
在布線的各階段中，總體布線有較大的靈活性，但對各區域或信號線上的串擾難以估計詳細布線可以精確地計算串擾，但靈活性太小，往往出現反復拆線重布，難以達到設計收斂相比之下，總體布線和詳細布線中間的階段既有一定的靈活性，又可以相對準確地計算噪聲，是解決串擾問題的理想時機。 -
The research on anycast routing protocol is the key of the performance of its services, but the work on this aspect is just at the elementary stage
而對anycast路由協議進行研究是確保該服務能否實現的關鍵，但是這方面的工作卻還處于起步階段。
分享友人