standard cell design 中文意思是什麼

standard cell design 解釋
標準單元設計
  • standard : n 1 標準，水準，規格，模範。2 旗；軍旗，隊旗；【徽章】標幟，標記；旗標，象徵。3 【植物；植物學】...
  • cell : n 1 小室，單室；隔間，艙；〈詩〉茅舍；（單個的）蜂窩，蜂房。2 〈詩〉墓穴，墓。3 （大修道院附屬的...
  • design : vt 1 計劃，企圖，立意要…。2 指定，預定；留給，留著。3 設計，草擬，擬定，籌劃；起草，畫草圖，打（...
  1. Abstract : a cad tool based on a group of efficient algorithms to verify, design, and optimize power / ground networks for standard cell model is presented. nonlinear programming techniques, branch and bound algorithms and incomplete cholesky decomposition conjugate gradient method ( iccg ) are the three main parts of our work. users can choose nonlinear programming method or branch and bound algorithm to satisfy their different requirements of precision and speed. the experimental results prove that the algorithms can run very fast with lower wiring resources consumption. as a result, the cad tool based on these algorithms is able to cope with large - scale circuits

    文摘:介紹了一個基於標準單元布圖模式的電源線/地線網路的輔助設計集成工具.它應用了一系列高效的演算法，為用戶提供了電源線/地線網路的設計、優化和驗證的功能.非線性優化技術、分枝定界演算法和不完全喬萊斯基分解的預優共軛梯度法是該工作的三個主體部分.用戶可以選擇使用非線性規劃的方法或者幾種分枝定界方法來滿足他們對于精度和速度方面的不同需求.實驗結果表明，文中所提供的演算法可以在很快的運行速度下實現更低的布線資源佔用.因此，在這些有效演算法基礎上實現的輔助設計工具具有處理大規模電路的能力
  2. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  3. Based on generation and processing of phase conflict graph, a new method is presented to fully and accurately verify the phase compatibility of dark - field standard cell layouts, which are produced according to conventional design rules

    摘要介紹了一套基於相位沖突圖的生成和處理的新方法，可以準確、全面地對由傳統方法設計的標準單元版圖（暗場）進行檢查。
  4. Standard guide for general design considerations for hot cell equipment

    熱電解池的通用設計方法標準指南
  5. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  6. Finally the design of rs decoder in this chip is described as an example of the hardware / software co - design based on asip, the construction and application of asip is also analyzed. the fourth chapter introduces the design flow using eda tools based on standard cell, then it presents the dft of this chip in detail which uses following techniques : full scan, bist and boundary scan to improve the fault coverage

    第四章，在對本晶元的基於標準單元eda設計流程進行了簡要說明基礎上，對本晶元採用的可測試性設計進行了詳細的分析和說明，本晶元中有機結合了多種可測試性設計技術：基於全掃描的方式、 bist測試技術、邊界掃描技術，保證了很高的測試故障覆蓋率。
  7. The thesis discusses how to design a chip, which works as a target pci device, and provides its semi - custom design method based on standard - cell library

    本文研究一種支持pci從設備總線協議的介面晶元的設計方法，並完成了其基於標準單元的半定製asic設計。
  8. The focus of our research in the low - power design of viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment

    從這里發掘功耗的潛力是很大的，主要通過優化演算法、優化邏輯結構來實現。
  9. Similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells. however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard - cell. because the router cannot impose the characteristic of the transistors in the standard - cell, it may reduce the performance of the whole chip

    通常，基於標準單元布圖模式將版圖綜合劃分成單元內與單元間兩個層次，以簡化晶元級自動版圖綜合問題的復雜性；但隨著晶元規模的不斷擴大，基於主要以手工定製的小規模標準單元，晶元級版圖綜合問題的復雜性不斷增大，且標準單元間布線無法充分利用單元內晶體管特徵，影響晶元的整體性能。
  10. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard - cell asic design realization in 0. 18 micron 6 - layer umc cmos technology

    由於上市的時間越來越關鍵，系統的自適應性和演算法的復雜度增大了，硬部件的重用也因此變得必要了。
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