stuck-at fault 中文意思是什麼

stuck-at fault 解釋
受干擾故障
  • stuck : stick 的過去式及過去分詞。stuck on 眷戀；愛上。 stuck-up 形容詞〈口語〉驕傲的，自高自大的，自以為了不起的；自私的。
  • at : 1 Air Transport（ation） 2 【電學】 ampere turn 3 antitank 4 Atlantic Time 5 alternative technolo...
  • fault : n 1 過失，過錯；罪過，責任。2 缺點，缺陷，瑕疵。3 （獵狗的）失去嗅跡。4 【電學】故障，誤差；漏電...
  1. With the development of manufacturing technology of digital integrated circuit, the voltage test method based on stuck - at fault model can not detect all the faults in modern integrated circuit

    隨著集成電路製造技術的發展，基於固定型故障模型的電壓測試技術越來越不能滿足高性能集成電路的需求。
  2. For the convenience of test, varied circuit chip defects caused by the production process are abstracted as all kinds of models. at present the commonly used fault models mainly consist of stuck - at fault, stuck - open fault, bridge fault, store fault, delay fault, etc. testing methods based on voltage testing mainly aim at stuck - at fault model and have also obtained satisfactory result in research for many years. bridge fault is tested easily by quiescent power supply current ( iddq ) testing method. in regard to stuck - open fault that is difficult to testd by quiescent power supply current ( iddq ) and voltage testing, it can is tested by the dynamic current ( iddt ) testing

    為了便於測試，我們將生產過程中集成電路出現的多種多樣的缺陷抽象為各種模型。目前常用的故障模型主要有:固定故障，開路故障，橋接故障，存儲故障，時滯故障等。電壓測試主要針對固定型故障模型，多年的研究也取得了令人滿意的結果; cmos電路中的橋接故障則宜用穩態電流測試方法（ iddq ）測試;對于電壓和穩態電流難以測試的開路故障，可以使用瞬態電流測試（ iddt ）的方法進行測試。
  3. The stuck - open fault is simulated concurrently using iddt testing with the test pattern pairs generated above. through detaching a pattern pair into two independent patterns, the stuck - at fault are simulated concurrently. simulation results show better fault coverage. the

    最後，針對iddt測試的可行性，我們通過利用pspice軟體對s208電路中的一些故障做了模擬，這些故障包括開路故障和延時故障。
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