substrate gate 中文意思是什麼
substrate gate
解釋
襯底柵-
This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n-type.
這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的P型襯底轉變成N型。 -
We studied the resurf, trench - gate, 3d - resurf ldmos. we designed the power switch ic based on epitaxial simox substrate, satisfying the requirements of the user. this ic can sustain 60 ~ 80v shutdown voltage overshot
在此基礎上，本文設計了性能滿足用戶要求的，基於esoi襯底結構的功率開關集成電路，該集成電路可承受60 ~ 80v的反向過沖電壓，並具有過流，過壓等保護電路。 -
Tddb and hce always take place simultaneously under device operation conditions. hot - carrier enhanced tddb effect of ultra - thin gate oxide is investigated by using substrate hot - carrier injection technique
在通常的工作條件下，氧化層的經時擊穿和熱載流子效應總是同時存在的。 -
The author ' s main contributions are outlined as following : first, the roles of hot electron and hole in dielectric breakdown of ultra - thin gate oxides have been quantitatively investigated by separately controlling the amounts of hot electron and hot hole injection using substrate hot hole ( shh ) injection method. the changes of threshold voltage have been discussed under different stress conditions
主要研究結果如下：首先，利用襯底熱空穴（ shh ）注入技術分別控制注入到超薄柵氧化層中的熱電子和空穴的數量，定量研究了熱電子和空穴注入對超薄柵氧化層擊穿的影響，討論了不同應力條件下的閾值電壓變化。 -
Problems about fabrication of sige - oi substrate, low - temperature gate oxidation and source / drain ion implantation are discussed after considering technology level and reported articles
然後用二維模擬軟體medici模擬，得到器件的閾值電壓約為- 0 . 1v ，泄漏電流很小。 -
Internal field generated by contact potential of gate electrode and substrate is considered to be responsible for the enhancement of c - v hysteresis. we first incorporate e - beam evaporation of hf with post thermal oxidation to fabricate hfo2 for the application of gate dielectrics
硅化物主要是由沉積過微溯博士裕文搏要程中hf和出的互擴散引起的，而熱氧化可以將其轉化成具有較高介電常數的硅氧化物hfxsiyo 。 -
The calculational result by exact solution shows that the substrate inject current is larger than gate inject current in the same condition. the influence of the thickness of sio2 and la2o3 on the tunneling current is given to compare much different thickness of sio2 and la2o3 tunneling current on the same equivalent oxide thickness ( eot ) condition
在等效氧化層厚度相同的情況下，比較了幾種不同的sio _ 2層厚度和la _ 2o _ 3層厚度結構的隧穿電流的大小，給出了sio _ 2層厚度和la _ 2o _ 3層厚度對隧穿電流的影響。 -
This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n - type
這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的p型襯底轉變成n型。
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