testability 中文意思是什麼

testability 解釋
可測試性 一個系統或組件有利於測試標準建立和確定這些標準是否被滿足的測試執行的程度。

  1. As one of the design for testability technology, boundary scan test ( bst ) fixes boundary scan cells between the device pins and core logics. thus, the bsc acts as the virtual test probe that carries out the test stimulus and captures the test response

    作為一種結構插入的可測性技術，邊界掃描測試（ bst ）技術將邊界掃描寄存器單元安插在集成電路內部的每個引腳上，其作用相當于設置了施加激勵和觀測響應的內建虛擬探頭。
  2. My design partitions the application in three basic conceptual ways : model - view - controller ( mvc ) architecture, multi - tier architecture and traditional modular decomposition. these make the whole system become a multi - tier component system, loose - couple horizontally and vertically, provide flexibility, reusability, testability and extensibility

    本文提出基於j2ee的erp應用系統，以三種基本概念方式來劃分應用系統：傳統的模塊分解方式；模型-視圖-控制器mvc （ model - view - controller ）體系結構；多層體系結構。
  3. Since the chip has interior sram and it ' s difficult and slow to test sram exteriorly, in chapter four we use the technique of bist in design of testability of sram, which makes it possible to test the memory at normal working speed

    由於片內有sram ，而sram的片外測試比較困難且速度較慢，所以文中第四章採用bist技術對sram進行了可測性設計，完成後可以用正常的工作速度對存儲器進行測試。
  4. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  5. We present a distributed application system based on j2ee and it makes the whole system become a multi - tier component system, loose - couple horizontally and vertically, provide flexibility, reusability, testability and extensibility

    本文提出基於j2ee的分散式應用系統使整個系統成為一個多層的組件系統，以實現系統橫向、縱向之間的弱耦合，使系統具備了靈活性、可重用性、可測性、可擴展性。
  6. A new tool to support design by contract is designed and implemented, which is named pkujdbct and can be used to support design for testability of components, and provide a basis for our future research on methods of contract - based design for testability of components

    設計並實現了一種新的合約式設計工具pkujdbct ，為構件的易測試性設計提供有力的支撐，並為今後進一步研究基於合約的構件易測試性設計方法打下了良好的基礎。
  7. Discuss the generation of test strategy for diagnosis based on information gain maximization and conditional entropy minimization. this approach can be used into the testability analysis and the optimization of test strategy for diagnosis

    研究了基於信息增益最大和基於條件熵最小的診斷測試策略生成問題，該方法可用於系統的可測性分析、診斷測試策略的優化等方面。
  8. Then a comparison is made according to their characters and the application scope of each method is determinate. from that we get the whole scheme of design for testability of dspc50, which is using boundary scan to improve the board - level testability of the chip and using full - scan in designing the nuclear circuit to reduce the difficulty of testing the chip

    在此基礎上得到dspc50的可測性設計的整體方案，即採用邊緣掃描設計提高晶元在板級的可測性，同時用全掃描思想設計晶元核心電路，以降低晶元本身測試的難度，即將晶元的全掃描設計包含入邊緣掃描系統。
  9. Analyses and modeling of testability based on multi - signal flow graphs

    多信號流圖的測試性建模與分析
  10. The requirement demonstration and ideation for testability design of new type amphibious armored vehicle

    新型兩棲裝甲車輛的測試性設計需求論證及構想
  11. The subject of this dissertation is the research on the design for testability in the design environment of system on a chip

    本論文的研究課題為片上系統（ systemonachip ，簡稱soc ）環境下的可測性設計方法學研究。
  12. Trial - use standard for testability and diagnosability characterisics and metrics

    試驗能力和診斷能力特性和度量的試用標準
  13. Not only the scan route solution, the built - in self - test solution and the boundary scan solution of design for testability are summarized, but also the applications and countermeasures of these 3 solutions are analysed and compared in details

    摘要綜述了超大規模集成電路的幾種主要的可測試性設計技術，如掃描路徑法、內建自測試法和邊界掃描法等，並分析比較了這幾種設計技術各自的特點及其應用方法和策略。
  14. With the high development of the quantum circuits, the testability of the circuits will become a very serious problem. the method of testability design for rt circuits is proposed in the end of this paper, which has high testability and low hardware cost. only adding one extra mos transistor and two control ports, it can detect all open and short faults in rt circuits

    隨著量子電路的飛速發展，由於其本身所特有的高集成度特點，電路的測試必然會成為越來越嚴重的問題，因此論文在最後就電路中常見的開路、短路故障提出了rt電路的可測試性設計方法，並針對具體的mobile電路進行了可測試性設計， pspice模擬結果表明達到了可測試的目的。
  15. Built - in test ( bit ) technique is an important approach to improve testability and diagnostic capability of equipments and devices greatly. the domain of bit application has extended from electronic equipments to mechantronic equipments. however, the high false alarm rate ( far ) is one of the important factors that prevent bit from being more extensively applied

    機內測試（ built - intest ， bit ）技術在提高武器裝備和機電系統的測試性、簡化維修過程和降低保障費用等方面發揮了重要作用，但虛警率高的問題一直阻礙著bit效能的充分發揮和更廣泛、更深入的應用。
  16. The main works are as follows : 1 ) we made the mathematics model of mixed - signal circuits based on the des theory to make the circuit states discrete. so we can unite the digital part and the analog part of the circuit to research the testability and the fault detection

    本文所做主要工作如下： 1 、本文利用des理論對數模混合電路進行數學建模，將電路狀態離散化，從而將電路的數字部分和模擬部分統一起來進行故障診斷和可測性分析。
  17. Abstract : constant components and output opened ports in the result of high - level synthesis lead to explicit redundancy in gate - level technology mapping. explicit redundancy can not improve the performance, but increases power consumption, enlarges circuit area and decreases its testability, so it should be removed. this paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability

    文摘:高級綜合結果中常量元件和輸出懸空埠導致門級工藝映射結果中存在顯式冗餘.顯式冗餘無助於提高電路性能，反而增加功耗，降低電路的可測試性，使電路面積增大，應予消除.文中提出了顯式冗餘的隊列循環優化演算法，完全消除了此類冗餘，從而有效地減少了生成電路的基片面積，提高了電路的可測試性
  18. In order to enhance the testability, reduce the maintenance costs of the electronic equipment, it is very important to develop a boundary - scan test system ( bsts )

    隨著具有邊界掃描結構的晶元在裝備中的大量應用，開發出實用的邊界掃描測試系統，對于提高裝備的可測試性，降低維護和保障費用具有重要意義。
  19. It is an important technical way by which the testability and the fault detection of mechatronic systems can be remarkably improved

    它是一種能顯著改善機電系統測試性與診斷能力的重要技術手段。
  20. For instance, extreme programming and test - driven development use some of these metrics to determine the testability of classes and methods

    例如，極限編程和測試驅動開發使用了這些度量中的一些來決定類和方法的可測試性。
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