time sharing circuit 中文意思是什麼
time sharing circuit
解釋
分時電路-
This paper researches and analyses the developments of web technology and magnetostrictive transducers from world wide region. the paper also analyes the characteristics curve of magnetostrictive transducers based on its equivalent circuit and researches the method how to make sure its syntony frequency and its electric simulation network parameters. at the same time, by using jsp technology, a magnetostrictive transducer electric simulation application is designed based on b / s three - tier system structure. the experiment data is fitted by curve fitting module. the equivalent input impedance of it with stimulate loop is separated based on the results of curve fitting and the syntony frequency and electric simulation network parameters of magnetostrictive transducers is determined by the input impedance. the method presented in this paper can determine the syntony frequency and electric simulation network parameters of magnetostrictive transducers with a better accuracy than the testing method of syntony & anti - synton y. further more, jsp, the advanced technology at current, has been used to realize a magnetostrictive transducer web electric simulation system. the system has good human computer interface and the function of resource sharing and information publishing. the research of this paper and its achievements have some practical merits in the researchful and applied fields of magnetostrictive transducer
用java編程語言編寫的曲線擬合模塊，對輸入的實驗數據進行了最小二乘法的曲線擬合；根據曲線擬合結果可從帶激勵線圈的磁致伸縮換能器的輸入阻抗中分離出磁致伸縮換能器鐵芯在無激勵電流時由機械振動形成的等效輸入阻抗，並由此輸入阻抗確定磁致伸縮換能器的諧振頻率及電氣模擬網路參數。本課題提出的方法與傳統的諧振?反諧振法相比，能更準確地確定磁致伸縮換能器的諧振頻率及其電氣網路參數。同時，採用當前比較先進的web技術，實現了基於jsp的磁致伸縮換能器web電氣模擬系統，該系統具有良好的人機界面和資源共享、信息發布功能。 -
Use cpld, we can get time sharing what need for circuit conveniency, simulate and validate it
對于電路所需的時隙，用cpld的分頻結構可以很方便得到並加以模擬驗證。 -
The serial a / d transformation and the channel isolation technology are adopted. eight - channel parallel data acquisition and test data time - sharing storage are realized. verilog hdl ( hardware description language ) is adopted to design the vxi register - based interface circuit and control circuit of each channel
以fpga （ fieldprogrammablegatearray ）為控制核心，採用串列a / d變換器和通道隔離技術，實現了8通道并行採集和測試數據分時存儲功能，利用veriloghdl （ hardwaredescriptionlanguage ）設計vxi寄存器基介面電路及各通道的控制電路。 -
In the process of design, the thesis using the circuit structure of inverter series within memory cell, and sharing read and write ports within multi - bit for the first time, solves dominoes effect for driving multi - read port problem, and reduces layout area of double - memory cell for about 40 %, respectively
在設計過程中，首次對位單元採用反相器級聯的電路結構，解決了由於驅動多讀出埠問題引起的電路驅動多米諾效應;首次採用了多位共享讀寫埠的電路結構，減小了雙存儲體40 %的版圖面積。
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