timing check 中文意思是什麼
timing check
解釋
時間檢查-
Based on the timing constraints event model of rtl ( real time logic ), the compiling algorithms for timing constraints event transform the problem of how to detect timing constraints event to the problem of how to find negative cycle in weighted directed graph, which is named as constraints graph. by simplifying constraints graph, the efficient detecting algorithms for timing constraints event have been developed, which not only has good time complexity but also can find events that violate timing constraints as early as possible. in order to verify the event detecting methods based on dynamic rules and to check its efficiency in application, experiment schemes are designed and performed on the implemented prototype system in linux environment
帶時間約束事件的編譯演算法以rtl （ realtimelogic ）事件模型為基礎，將帶時間約束事件的檢測轉化為在帶權值的有向圖（此即受限圖）中尋找負圈的問題，它通過化簡受限圖得到最小有效約束集；運行時事件檢測演算法在最小有效約束集上檢查事件的時間約束，不但有較好的執行效率，而且能盡早地發現違反時間約束的事件。 -
On the other hand, we accomplished the asic design flow successfully based on the fpga design. we have made the most use of various optimization methodology and simulation tools include dynamic simulation, static timing analyzing and post simulation. at last this design net list was past to layout design team in order to check its electronic characters
在我們的asic流程中，首要的因素是在fpga驗證其正確性的基礎上對速度與面積進行科學有效的平衡，在成本和性能中間取得良好的結合點，運用先進的eda設計工具和演算法對設計進行綜合優化（ synthesis ） ，動態時序分析（ dynamicsimulation ） ，靜態時序模擬（ sta ）到自動布局布線（ apr ）之後將寄生參數反標回前面的步驟進行更精確的判斷和分析，最後交給版圖設計人員進行版圖設計和優化。 -
One timing verification approach with the aid of the timing check system
一種藉助時序檢測系統進行時序驗證的方法 -
The digital one includes spec, verilog coding, simulation, synthesis, floorplan, routeing, static timing analyze and drc / lvs check
數字電路設計流程則包括：制定spec ， verilog代碼編寫，模擬，邏輯綜合，布局，布線，靜態時序綜合和drc lvs檢查。 -
Check the ignition timing
檢查電子點火器正時。 -
Firstly, the discrete multi - tone processing in an adsl central office - side interface card is detailedly introduced. the processing mainly includes timing, framing, interleaving, forward error correction, cyclic redundancy check, constellation encoding, inverse fast fourier transform processing, prefixing, d / a converting, and amplifying. secondly, a kind of interface named utopia level 2 is used as the network interface, with which many adsl devices are linked with one atm layer
本文比較詳細地闡述了數字用戶線接入模塊（ dslam ）開發方案中， adsl局端介面模塊的dmt編碼與調制過程，討論了其組網應用方式以及基於atm的網路側介面utopia2技術，分析了adsl與其它寬帶接入技術的相互聯系和優缺點，並介紹了方案中所採用的一些關鍵技術，包括在線插拔技術、系統同步啟動和故障自動重起技術以及高速數字信號完整性的保證技術等等。 -
By this means, the study of animal behavior has become more convenient and efficient. compared to the inconvenience and lack of precision of traditional recording methods, e. g., timing by stop watch and recording data on a check sheet by hand, the adoption of a computerized event recorder program provides many advantages, e. g.,
傳統式的行為數據記錄方法由於不方便和不精確，例如使用計時馬表和檢查表以手抄寫的記錄方式，目前大多採用電腦化的事件記錄器程式來取代，相較之下，電腦程式的優點為：持續時間 -
It has a static yoke. i ' ll double check the draw stop timing. would draw stop timing affect left / right impact
本來纜索就是靜態卡位的.我想再查看一下偏心輪拉停定位的同步問題.吃不準，拉停定位的同步，是否真的影響到命中點的左右偏差
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