timing chip 中文意思是什麼
timing chip
解釋
計時基片-
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
Application of one - chip computer control thyristor and replacing combination for timing compensation adjustment enable it to realize fast non - contact adjustment
採用單片機控制晶閘管，切換組合進行適時補償調節，實現了快速無觸點調節。 -
The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。 -
Patented structure, ptc heating ; hot air blowing for quick dry ; microcomputer chip control, led digital display, optional timing within 3 hours, 500w, provide dismountable hangers, stand feet, mainframe and umbrella parts, hanger buckle for optional positioning and attached with packing bag for storage when unused
專利結構，通過ptc發熱，風葉吹出熱風將衣服晾乾，微電腦晶元控制，電子led發光數碼顯示， 3小時內任意定時，功率500w ，可提供可拆卸的衣架，支腳?主機?傘架可拆卸，可任意定位的衣架扣，附有包裝小袋，便於不使用時收起包裝。 -
Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。 -
It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation
並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。 -
The whole circuit ' s timing generation and synchronization was realized with cpld. as the channel of data transmitting, pof can isolate high voltage part and low voltage part efficiently. at the same time, a single chip processor was used to design a digital meter for the fiber current transducer
系統採用cpld實現整個工作電路的時序發生和同步協調，利用光纖實現高壓部分和低壓部分的完全電氣隔離和實現信號傳輸，採用單片機技術實現混合式光纖電流互感器專用數字顯示儀表的設計。 -
It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。 -
However in soc or high performance cpu an in - chip high quality clock is required to guarantee the timing of all chips
而soc或者高端的cpu一般都採用同步的數字電路設計，時鐘是整個晶元時序的保證。 -
It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface
本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。 -
Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment
Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。 -
Then describes the 4 function modules in vhdl, the vhdl programs have passed compile and debug in maxplus ii, the results of function simulation and timing simulation all prove that the design is correct, at last, maxplus ii generates a netlist file which can be download into chip
然後使用vhdl硬體描述語言對四大功能模塊進行描述，在maxplus環境下編譯、調試通過，功能模擬和時序模擬結果證明設計正確，最後生成可下載的網表文件。 -
The main work and achievements are as follows mcs - 51 microcontroller is studied. the result of the research is included mcs - 51 microcontroller work princip instruction system timing analysis feature picking up ; etc mcs - 51 microcontroller chip has been anatomized
本論文的目的是設計mcs ? 51單片機晶元，主要工作和取得的成果如下：對mcs ? 51單片機進行分析研究，包括mcs ? 51單片機工作原理、指令系統、時序分析、特徵提取等。 -
This paper briefly introduces design method of the multi - function timing control unit. it is made of 89c51 and other integrate circuit chip, and produce the frame diagram for monitoring program
摘要介紹了一種多功能定時控制器的設計方法。它是由89c51單片機和幾個主要的集成電路晶元構成。並給出了監控軟體的結構框圖。 -
The misc logic module can capture and lock the errors of processor local bus and on - chip peripheral bus. these errors can be shown by light - emitting diode light. the chipscope _ ila core is used for debugging the fpga logic and timing
而輔助邏輯主要是用來捕獲並鎖定powerpc ~ （ tm ） 405的處理器局部總線（ plb ）和片上外圍總線（ opb ）的錯誤，並通過led燈進行顯示。 -
It can prevent the output timing of the column driving signal from coinciding at neighboring columns, eases the concentration of supply current, and reduces power consumption, integrate the idea of alternating current driven method and gray - scale plus shifting modulation, we designed the software which includes both of the functions for oled driving chip
為了減小了顯示系統在灰度初始輸出時間對電流供應的集中需求，在參考相關專利后，更改了專利中提及的一些比較器的函數關系，在波形模擬上實現了oled顯示數據8級灰度的移位調制輸出。 -
In this paper, the digital image real - time processing system was a very important part of fed driving circuit system. altera fpga chip was used to complete operation on reading and writing and timing control of fed image data. the image process algorithms mainly used gray - level transformation in the theory of image enhancement, and the algorithm realized luminance non - uniformity control, gray - level non - linear correction and automatic power control for fed
本文設計的基於fpga技術的數字圖像實時處理系統是fed驅動系統中的重要組成部分，其核心部分採用了altera公司的fpga晶元，實現對fed圖像數據讀、寫操作和時序控制等，而圖像處理的演算法部分主要是利用圖像增強技術理論中的灰度變換方法，實現對fed的亮度非均勻性控制、灰度非線性校正以及fed的自動功率控制。
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