timing circuit 中文意思是什麼
timing circuit
解釋
計時電路定時電路-
The main loop of the welder uses a thyratron transistor non - contact switch circuit, quick and reliable close time, accurate timing of welding, high precision of welding, good repeatability, bring a high quality welding
焊機主迴路採用晶閘管無觸點開關電路，關斷時間快、可靠，焊接定時精確，焊接精度高，重復性好，可實現高品質焊接。 -
In the experimental system apd transferred laser pulse to weak electrical current. after two - level amplification we got a voltage pulse that had a enough amplitude to be applied, the timing point was discriminated by the constant - fraction timing discriminator circuit. timing circuits transferred the pulse flight time to digital signal accurately
實驗系統採用apd作為光電傳感器，將激光脈沖信號轉變為微弱電流脈沖，經過兩級放大后，信號變為幅度較大的電壓脈沖，經過時點鑒別電路分別確定計時起點和終點后，由計時電路來精確測量兩個時間點之間的時間間隔。 -
A type of receiver circuit and timing circuit which can be applied in high - speed laser range - finder is discussed in this paper
本論文詳細討論了一種可實現高速激光測距的接收電路和計時電路。 -
Implementation of programmable logic device in timing control circuit
定時控制電器的可編程邏輯器件的實現 -
Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed. compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high - speed circuit design
在時序邏輯電路精確定時方面，從時序電路的敏化定理出發，使用本文給出的條件可敏化概念，通過對通路敏化性質的判斷建立了一種新的單周期敏化的時序電路最小時鐘周期精確確定方法。 -
This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15
該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。 -
The use of time delays on these vehicles helps to eliminate transmission and motor damage by providing even and controlled acceleration. the delay is adjustable between 0 to 5 seconds and can be wired independently of other delays or alternatively these delays can be wired in cascade so that it is necessary for the first delay to switch on before the following commences timing etc. suppression is included in the delay circuit to prevent damage by voltage transients
延遲開關可以調整延遲時間0 ~ 5秒，並可連接數個延遲開關來逐步控制連續動作之時間（復數連接時，第一個開關要啟動接下來的開關才會跟著動作）避免電動車起動初期之電力脈沖，達到平順的起步動作，可預防電壓無端變動造成之電路故障 -
The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions
本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。 -
The whole circuit ' s timing generation and synchronization was realized with cpld. as the channel of data transmitting, pof can isolate high voltage part and low voltage part efficiently. at the same time, a single chip processor was used to design a digital meter for the fiber current transducer
系統採用cpld實現整個工作電路的時序發生和同步協調，利用光纖實現高壓部分和低壓部分的完全電氣隔離和實現信號傳輸，採用單片機技術實現混合式光纖電流互感器專用數字顯示儀表的設計。 -
After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages
它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。 -
In this thesis, the research on short - range high accuracy range finding system, which is inexpensive and compact, is done. to design the laser transmitter and the timing circuit is the main task
本文旨在針對成本低、體積小的高精度短程激光測距系統開展研究工作，主要任務是設計與實現脈沖激光測距系統中激光發射器電路和計時電路。 -
An algorithm of path - based timing optimization by buffer insertion is presented. the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation. and heuristic method of buffer insertion is presented to reduce delay. the algorithm is tested by industral circuit case. experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
提出了一種基於路徑的緩沖器插入時延優化演算法，演算法採用高階模型估計連線時延，用基於查表的非線性時延模型估計門延遲.在基於路徑的時延分析基礎上，提出了緩沖器插入的時延優化啟發式演算法.工業測試實例實驗表明，該演算法能夠有效地優化電路時延，滿足時延約束 -
The definition of high - speed circuit design as well as the signal integrity and timing problems in this design was introduced
摘要介紹了高速電路的定義以及在高速電路設計中存在的信號完整性、時序問題，詳細分析了產生這些問題的原因。 -
Finally the timing problems in high - speed circuit design were analyzed and the conditions of timing design in source synchronous clock system were derived
最後分析了高速電路設計中時序問題，給出了源同步時鐘系統中時序設計應該滿足的條件。 -
Systematic inside have adopted the method of time base with timing circuit storing annual examine information, then the traffic management department and the automobile operation unit can manage or supervise automobile easily
系統內部採用了時基電路定時的方法儲存年檢信息，便於交通管理部門以及汽車運營單位對汽車進行管理和監督。 -
Based on the pre - amplifier circuit board of the data acquisition & control ; system of the industrial ct, this paper explains how to use cpld to control the timing of ddc112
摘要結合工業ct的數據採集控制系統的前置放大器電路，分析了利用cpld對電流積分型前放晶元ddc112進行邏輯控制的方法。 -
The limitations of schmitt toggle circuit, composed of 555 timing circuit, is discussed, a improved schmitt toggle circuit is given, and proved by using theory and experiment
摘要論述了常用555定時器構成的施密特觸發器電路的局限性，給出了施密特觸發器的改進電路，並用理論和實驗加以證明和驗證。 -
The codetest performance tool provides an in - circuit software timing measurement for the entire program at one time
性能工具提供一次用於整個系統的在線軟體計時測量。 -
In order to reduce cost as low as possible, we use another novel method, designing timing circuit for lcd by fpga to control the display of lcd
本文採用一種新的顯示控制方式:即直接用fpga產生lcd所需要的顯示控制時序，控制數據的傳輸和顯示。 -
Variety of timing methods are analyzed and compared, then the scheme of this thesis is made. by combining the traditional counting method with time stretching method, the accuracy and resolution of timing circuit can be greatly improved
基於對已知的幾種計時方法進行的分析和比較，本文選用傳統測量方法與時間線性展寬技術相結合的方法實現時間間隔的高精度測量。
分享友人