timing cycle 中文意思是什麼
timing cycle
解釋
定時循環-
Some inner clocks seem to be set to a timing cycle of about twenty - four hours. these are called circadian rhythms
一些生物鐘似乎是按照24小時的周期設定的，這些現象叫做生理節律。 -
This paper introduces common background knowledge of intersection, mainly describes traffic control design principle, such as signal timing and lane channelization. it also summarizes the same point between signal timing and lane channelization in nature and illustrates that it is optimal cycle length and signal phase that is the critical part of signal timing
=本文介紹了交叉口的一般背景知識，重點闡述了平面信號交叉口的交通控制的設置原理，包括信號配時原理和路口渠化原理，概括了信號配時和路口渠化原理的本質相同點。 -
Sometimes bowlers will get a little lazy with their push away. this will shorten the swing cycle and tend to make the bowler have early timing
有時球員推球時有點無精打采，這樣會縮短擺?圈，進而造成過早的時間差。 -
Based on the timing constraints event model of rtl ( real time logic ), the compiling algorithms for timing constraints event transform the problem of how to detect timing constraints event to the problem of how to find negative cycle in weighted directed graph, which is named as constraints graph. by simplifying constraints graph, the efficient detecting algorithms for timing constraints event have been developed, which not only has good time complexity but also can find events that violate timing constraints as early as possible. in order to verify the event detecting methods based on dynamic rules and to check its efficiency in application, experiment schemes are designed and performed on the implemented prototype system in linux environment
帶時間約束事件的編譯演算法以rtl （ realtimelogic ）事件模型為基礎，將帶時間約束事件的檢測轉化為在帶權值的有向圖（此即受限圖）中尋找負圈的問題，它通過化簡受限圖得到最小有效約束集；運行時事件檢測演算法在最小有效約束集上檢查事件的時間約束，不但有較好的執行效率，而且能盡早地發現違反時間約束的事件。 -
It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。 -
Then the designs of modules mentioned in the scheme are discussed in detail. the main contents of the dissertation include : 1. to satisfy the need of a16 / d16 single - cycle and block data transfer capability, the method of the state machine and diagram are adopted. the arbiter, requester, interrupter, interrupter handler modules are also implemented by use of the state machine. these modules are verified theoretically by using timing simulation
本文具體工作如下: 1 .用狀態機和電路圖的方式實現了vme總線a16 / d16單周期數據讀寫和塊傳輸功能;並用狀態機設計了vme總線請求器，總線仲裁器，中斷器和中斷處理器等，並進行了時序模擬。 -
For decades, scientists have tracked the solar cycle and appearance of sunspots, but they have been unable to accurately predict the intensity or timing of solar storms, which increase as the number of sunspots increases
最近幾十年來，科學家一直在跟蹤太陽活動周期和太陽黑子的出現。但是，他們至今仍然無法準確預測太陽風暴的強度和時間。 -
The business presence was minimal, and this largely reflected the timing on the technology adoption cycle
商業代表很少，這在很大程度上反映了技術採用周期的變化。 -
Pkc - mediated control of these transitions can be negative or positive, depending on the timing of pkc activation during the cell cycle and on the specific pkc isozymes involved
Cki是近年來分離得到的一類很重要的細胞周期調控蛋白，這些蛋白在體外通過與cdk 、 cyclin或cyclin - cdk復合物的結合，抑制cdk的活性，進而抑制細胞周期的進程。 -
Based on the single cycle detector, the finite cycle detector is proposed for the detection of phase - coded signals. the finite cycle detector has a good performance under unknown the spreading code sequence, initial phase, spreading code timing epoch
針對相位編碼信號的檢測，提出了基於單循環檢測器的有限多循環檢測器，可在沒有編碼序列、初相、編碼序列初始時間等信息的情況下，取得理想的檢測效果。
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