uart 中文意思是什麼

uart 解釋
串口管理晶元
  1. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  2. In the project, the work completed by the author is as followed : ( 1 ) answer for events " transmition, which are transmitted to application programs, and correspondly dealt ; ( 2 ) answer for all of the handware drivers, included lcd display driver, flash driver, e2prom driver, sound driver, gsm status monitorer driver, keyboard driver, uart driver, real - time controller driver, hung - up monitorer driver ; ( 3 ) answer for all problems related with hardware drivers ; ( 4 ) answer for the tools for write data to flash, such as programs, font libraries

    該項目中，本人完成了以下幾方面的工作： （ 1 ）負責所有消息的驅動，使上層應用程序能夠接收到底層硬體設備產生的消息，並做相應處理； （ 2 ）負責所有硬體驅動程序的設計和調試。驅動程序包括lcd顯示驅動、 flash驅動、 e ~ 2prom驅動、聲音驅動、 gsm模塊狀態監控驅動、鍵盤驅動、串口驅動、實時鐘驅動、電源管理、摘掛機檢測驅動，共10部分。 （ 3 ）負責解決遇到的所有與驅動相關的問題。
  3. Application of navigation solution chip of uart communication based on nios

    的串口通信在解算晶元中的應用
  4. During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed

    在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。
  5. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  6. Last on the hardware of mainboard, the boot table which is used in boot loader, analogical uart and program of strapdown system are completed by assemble language and c language

    最後，在系統硬體電路板的基礎上，以tms320c3x匯編語言和c語為工具，編寫了用於程序引導裝載的boot文件，軟體實現了uart和捷聯演算法。
  7. The project use " top _ down " technology to develop core by dividing uart according to it ' s function

    本課題採用top _ down設計方法學，通過對系統按功能劃分模塊來進行設計。
  8. The main process includes following : system design, module design, function simulation, time simulation and hardware verification. the whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of uart and the requirement of design. the module design is to design inner circuit structure of each module and uses verilog language to code the code

    系統設計是基於uart的實現演算法和設計指標要求，對系統劃分模塊以及各個模塊的信號連接;模塊設計是設計出每個模塊的功能，並用verilog一hdl語言編寫代碼來實現模塊功能;功能模擬和時序模擬使用的工具是以dence的nc _ veri109 ，首先對系統的每個模塊進行功能和時序模擬，模擬通過之後，將整個系統的代碼在外部的輸入埠加上激勵，對整個系統進行功能和時序模擬;硬體驗證是用fpga對系統進行了功能驗證。
  9. Two uart ports and one dsu port

    32kb指令緩存器及16kb數據緩存器
  10. There are also the power - on circuit for gsm module, indication circuit, the uart to pc, etc. the mcu program, written with c51 language, include gps position, alarm of dilapidation, asynchronous communication and sms, clock management, etc. after development, the mts " capability had been tested

    另外還包括gsm的開機電路，指示電路，與pc相連接的串口等等。單片機軟體選擇了c51語言進行設計，包括gps觀測、崩塌傳感器報警、異步通信和短消息、時鐘管理等模塊。在完成終端的研製后，對儀器的性能進行了檢測。
  11. Is the uart channel number connected to the csr chipset

    是連接到csr晶元組的uart通道號。
  12. Uart receiver - transmitter section

    通用異步收發機接收機
  13. Uart double buffering

    通用異步收發機雙緩沖
  14. Based on s698 technology, obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller, etc. the bus interfaces is composed of i2c spi magnetic card interface and ic card interface. obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition

    Obt - devsys - s698是s698系列嵌入式處理器開發板中的一員，其上包括：具有32 64 - bit浮點運算單元的32 - bit嵌入式處理器，主頻160mhz ， sram存儲器， flash存儲器具有三路uart介面，一路ps 2介面， led發光二極體控制電路，中斷操作按鈕其外擴總線包括i2c總線介面spi總線介面磁卡介面智能卡介面等。
  15. Microcontroller msp430 f149 ( texas instrumentation corporation ) has embedded a 12bit a / d converter, two uart interfaces for local communication and a hardware multiplier for digital filtering

    單片機採用了ti公司的超低功耗msp430f149 ，利用其內帶的12位a d和串列口來完成a d轉換及數據通訊。
  16. For a board with built - in gsm gprs support for example, a board with a siemen s mc - 45 module wired to a uart channel, the legacy serial driver can drive the link

    對于內置gsm / gprs支持的母板（例如，一個帶有連接到uart通道的siemen mc - 45模塊的母板） ，傳統的串列驅動程序就能驅動這個鏈接。
  17. As can 、 lin 、 uart 、 van, there are lots of car protocol coming out. among them, lin gives the whole network technology new energy and shows us a cheap and stabilized protocol. in this background, faw - volkswagen use the lin bus in the car comfort system, and it is a special word in the car, it mainly control the windows - lifter 、 locks - closedown 、 top lighting - control 、 and baggage trunk.

    從lin總線的實現原理及舒適系統的組成結構入手確定了系統的測試內容;根據測試的內容確定了軟硬體的選擇，並進行了測控系統的整體結構設計和連接，完成了測試臺的搭建和調試;最後按照所要測試的步驟編寫了上下位機軟體。
  18. By the uart and rs232, devising the communication circuit with pc. 7. by the way of oversampling, making the system stabler

    使用了c8051f021的uart口和pc機的rs232口，設計了sw2000和上位機進行通信的電路。
  19. Based on above - mentioned schemes, the power detection system based on tms320vc5410 is designed, which realizes collection, a / d, digital signal processing. keyboard. display and uart ? the ad73360 gather chip commonly used in power system is used in front of the power detection system, and the circuit of frequency multiplication phase - locked is consisted of phase - locked loop device ? d4046 and frequency division device cd4060 to produce the gather signal of ad73360 frequently, the gather wave and re sult can be displayed on lcd

    基於上述方案，本人設計開發了基於tms320vc5410的電力採集檢測系統。基本實現了採集、 a d轉換、數字信號處理、鍵盤顯示、異步通信等系統軟硬體設計。該系統前端採用電力系統常用的ad73360採集晶元，鎖相倍頻電路由鎖相環cd4046與分頻器cd4060一起構成，產生ad73360採集觸發信號。
  20. Uart universal asynchronous receiver transmitter

    通用異步接收發送裝置
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