very high speed logic 中文意思是什麼
very high speed logic
解釋
超高速邏輯-
With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit
在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。 -
As a research trial for this thesis, we designed a real circuit based on cpld ( complex programmable logic device ) by vhdl ( very high speed integrated circuit hardware description l anguage ) for the hardware algorithm for euclidean distance transform with multilayer design method, called top - to - down
一down ）的方法，設計了一個基於復雜可編程邏輯器件cpld （ co哪lexprogammablelogiedeviee ）的基本電路，用以驗證基於硬體的歐幾里德距離轉換演算法的各項性能。 -
Very high speed logic
超高速邏輯 -
In this article, we study the implemetation of fpga for elliptic curve digital signature algorithm. based on number thesis 、 abstract algebra and complex thesis ， integrated information theory 、 cryptography and some specific relevant algorithm ， we ascertain the implementation of ecdsa for hardware project ： according to the design idea of hiberarchy and modularization, we adopt very high speed ic hardware description language ( vhdl ) as design input and simulate the design in every level and every model for the correct of the fundamental design. after finish the top design, we perform the whole simulation. then ， we carry out the timing simulation after the logic synthes and layout
本文從實際應用出發，研究了橢圓曲線數字簽名演算法的fpga的實現：以基本的數論理論、抽象代數和復雜度理論為依據，結合信息論、密碼學的一些知識以及一些具體的相關演算法，確定了ecdsa的硬體實現方案：按照層次化、模塊化的設計思想，採用硬體描述語言vhdl作為設計輸入進行ecdsa的硬體設計；在每個設計層次和每個模塊都進行了模擬驗證，得以保證底層設計的正確性。在確保每個模塊的設計正確后，完成對電路的頂層設計，進行總體的模擬。 -
The most prominent characters of our system are, ultra - high frequency, ultra - high speed of circuit and the very complex configuration of logic circuit
100gs / s的等價采樣系統的特點是電路頻率高、速度快、時序要求嚴格。 -
The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation
在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。 -
By now, the speed of logic computation in processing units is very high with general cmos technics
另外，為了測試方便，我們將輸入fifo設定為無窮大，避免的對fifo的不斷操作，進一步加快了模擬速度。 -
As the application of distributed computing is used much more widely ， distributed database becomes a significant part of information management it avoids a lot of disadvantages of conventional centralized database ， and is applicable to many situations distributed database is a set of data which is the unity logic ， but in fact these data is located on different sites it is of high availability ， easy expansibility ， high concurrency ， high efficiency and etc in distributed system ， data redundancy is a method to improve the speed of query and the availability of system distributed query should shield the lower level details of data redundancy from end users ， distributed transaction should ensure data from disaccord this paper introduces basic conceptions of distributed database firstly ， discusses distributed transaction and concurrent control ， describes the development prototype mysql ’ s characters ， architecture and executive mechanism ， then shows the skeleton model of dpsql and exposes the strategy and algorithm of distributed query and distributed transaction ， at last analyzes the extra expenses and response delay of distributed processes this paper exposes the implementation mechanism of distributed query and distributed transaction emphatically distributed query uses the strategy of “ read one ， write a11 ” s0 in such a system if user ’ s requests are read - - only for the most part and the distribution of data redundancy is plausible ， efficiency is very high distributed transaction uses two - 。 phase commit protocol to ensure the consistency of global data ， which has less communication overhead
分散式查詢需要向用戶屏蔽數據冗餘分散的底層細節，分散式事務處理要保證全局數據完整，這都是傳統集中式數據庫不曾面臨的問題。本文首先介紹了分散式數據庫的概念性問題；接著討論了分散式事務涉及的定義及演算法；然後描述了dpsql的原型mysql的特性、結構和執行機制；繼而給出了dpsql的梗概模型，闡述了實現分散式查詢和分散式事務處理的策略及演算法；最後分析了進行分散式處理給系統增加的額外開銷和客戶端的額外響應延遲。本文重點描述了分散式查詢和分散式事務處理的實現機制，分散式查詢採用」讀一個寫全部」的本地優先策略，在讀操作頻繁的系統中，只要庫的分佈合理，單機效率極高，幾乎無任何附加開銷和延遲，而以整個系統的角度看來，吞吐量就更是優于單機系統；分散式事務處理採用兩階段提交協議，通信次數較少並能確實保證副本一致。
分享友人